From patchwork Thu Mar 13 13:03:50 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 14014976 X-Patchwork-Delegate: bhelgaas@google.com Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DF497268C7A; Thu, 13 Mar 2025 13:03:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741871033; cv=none; b=VvfbP/uT/49RyXGUop9NjhvEWJoDSEiMPbQx5rzXKIP53VpftoAwhFSIt4EV1LvQJFrzyzV2LR12LI+/ISBVaxpRt7wEmkoVB8vrWDApk92X33elKZmmLawjt4JfzwCiHdeCSXI/74yW6J3llM+5fK5UjgnwltSqhVoQZ7/QTCw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741871033; c=relaxed/simple; bh=x5cX0aoOdbYTPk45mqAt6KtNcA84j7hnJw1NaQmAzGM=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=mMyvnITd3pIt26VrhP5zEV0T98NpUKOYoFrelcOJiJbHy9Ep15GwVdg+mhxjCw/+RG9zMmTBqAjYD1/1ZiaXmmiPmxrKLcIqHV3YhhUeAv9MMFrnMWV9Ltta/L9zuVF0cW0WOMwkGW0TPWiBSpmpQqejVQgcqkkJy8paiPzusl0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=NtpHq2hS; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=L50Mu6hV; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="NtpHq2hS"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="L50Mu6hV" Message-ID: <20250313130321.898592817@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1741871030; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=JS2z1O/KmW5u4BttxakywuyzKwIcG0AVCKTp1FgyzQM=; b=NtpHq2hSNMc2ZG3+w6P9RdUzxcKjLVSGDmgYPbToNCFsBogvedVNfySCnN7SP2aoBtfs4r tEwFy8e6VW1LGypRr4R/mWYy3a/eqbhtTMGdjSLUXa80UJq81DVCvN3FJC11ERnN1rKUvs nU0AlR+MSS3WCaYYTUWu/aagSqKone0qdBrqNw5mCA7wtkd3xRpcOUEu/oQDTAoJvWdbEZ EhtUAeoVggaBJZ/pqOVH2nJDbMiYo7/nJVlv2s5UIK9tVvqo83BBAJwdCfnjJOTWMIcc2r AEDt34SE+EEznogy39zM3HCpfpEEIzvYy8Nd7MebnCw9qI9U5iVt2YiYbwwlGA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1741871030; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=JS2z1O/KmW5u4BttxakywuyzKwIcG0AVCKTp1FgyzQM=; b=L50Mu6hVS6WjSGZ8VyPsrl7KULe+YlyE/ssnhQL2nlNwFfgabUxuKuEKKCQpxXnp+VFwUg TOSQQ86lMrXluZCg== From: Thomas Gleixner To: LKML Cc: Marc Zyngier , Bjorn Helgaas , Wei Huang , linux-pci@vger.kernel.org, Peter Zijlstra , Nishanth Menon , Jonathan Cameron , Dhruva Gole , Tero Kristo , Santosh Shilimkar , Logan Gunthorpe , Dave Jiang , Jon Mason , Allen Hubbe , ntb@lists.linux.dev, Michael Kelley , Wei Liu , Haiyang Zhang , linux-hyperv@vger.kernel.org, Manivannan Sadhasivam , "James E.J. Bottomley" , "Martin K. Petersen" , linux-scsi@vger.kernel.org, Jonathan Cameron Subject: [patch V2 08/10] PCI/TPH: Replace the broken MSI-X control word update References: <20250313130212.450198939@linutronix.de> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Thu, 13 Mar 2025 14:03:50 +0100 (CET) The driver walks the MSI descriptors to test whether a descriptor exists for a given index. That's just abuse of the MSI internals. The same test can be done with a single function call by looking up whether there is a Linux interrupt number assigned at the index. What's worse is that the function is completely unserialized against modifications of the MSI-X control by operations issued from the interrupt core. It also brings the PCI/MSI-X internal cached control word out of sync. Remove the trainwreck and invoke the function provided by the PCI/MSI core to update it. Signed-off-by: Thomas Gleixner Acked-by: Bjorn Helgaas Cc: Wei Huang Cc: linux-pci@vger.kernel.org --- drivers/pci/tph.c | 44 +------------------------------------------- 1 file changed, 1 insertion(+), 43 deletions(-) --- a/drivers/pci/tph.c +++ b/drivers/pci/tph.c @@ -204,48 +204,6 @@ static u8 get_rp_completer_type(struct p return FIELD_GET(PCI_EXP_DEVCAP2_TPH_COMP_MASK, reg); } -/* Write ST to MSI-X vector control reg - Return 0 if OK, otherwise -errno */ -static int write_tag_to_msix(struct pci_dev *pdev, int msix_idx, u16 tag) -{ -#ifdef CONFIG_PCI_MSI - struct msi_desc *msi_desc = NULL; - void __iomem *vec_ctrl; - u32 val; - int err = 0; - - msi_lock_descs(&pdev->dev); - - /* Find the msi_desc entry with matching msix_idx */ - msi_for_each_desc(msi_desc, &pdev->dev, MSI_DESC_ASSOCIATED) { - if (msi_desc->msi_index == msix_idx) - break; - } - - if (!msi_desc) { - err = -ENXIO; - goto err_out; - } - - /* Get the vector control register (offset 0xc) pointed by msix_idx */ - vec_ctrl = pdev->msix_base + msix_idx * PCI_MSIX_ENTRY_SIZE; - vec_ctrl += PCI_MSIX_ENTRY_VECTOR_CTRL; - - val = readl(vec_ctrl); - val &= ~PCI_MSIX_ENTRY_CTRL_ST; - val |= FIELD_PREP(PCI_MSIX_ENTRY_CTRL_ST, tag); - writel(val, vec_ctrl); - - /* Read back to flush the update */ - val = readl(vec_ctrl); - -err_out: - msi_unlock_descs(&pdev->dev); - return err; -#else - return -ENODEV; -#endif -} - /* Write tag to ST table - Return 0 if OK, otherwise -errno */ static int write_tag_to_st_table(struct pci_dev *pdev, int index, u16 tag) { @@ -346,7 +304,7 @@ int pcie_tph_set_st_entry(struct pci_dev switch (loc) { case PCI_TPH_LOC_MSIX: - err = write_tag_to_msix(pdev, index, tag); + err = pci_msix_write_tph_tag(pdev, index, tag); break; case PCI_TPH_LOC_CAP: err = write_tag_to_st_table(pdev, index, tag);