From patchwork Fri Mar 21 12:14:41 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: George Moussalem X-Patchwork-Id: 14025324 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6E5D5223321; Fri, 21 Mar 2025 12:14:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742559286; cv=none; b=pP6JVcW1D5K/rJ52R0D4qkb5pwH5BOd4uK6xUcaWZLgzo2fzls+dfJ+ee5gnAPi7X35G65xZJnLJ19qFQinEHFQuQTNloczjto8ZyjVfNVg/IDug+iMS4ymewKfUAOqDosS7BRO20x4I44xGMxExpJ3JEiFxdd3/ccPLvVK3AQc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742559286; c=relaxed/simple; bh=Vlq0R7cLd+B8V83Bai1T9Yowc+PdKkhwH/55AXdKJTM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pBrSwvstDzisNUVhnoLztQOynsgkdQOPbI7reuXGs+T5M+p/SnLWgKjyzL154/tNdzkuL1/jeUwrGitadgSrvnpXhXdEzmTsdCuGNKNBvw8Wl8gMsN13XEZd/xVIOQcDAeAG9X5ZH+FckBa98FFWNQBTwZHto2Evifm1FXiV9KY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=hQUC2pdv; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="hQUC2pdv" Received: by smtp.kernel.org (Postfix) with ESMTPS id 1AE04C4CEF8; Fri, 21 Mar 2025 12:14:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1742559286; bh=Vlq0R7cLd+B8V83Bai1T9Yowc+PdKkhwH/55AXdKJTM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=hQUC2pdvOK2eAhECZJsC5zsh+Zw9Gt7XC8tT0XAKFkpYovLF4T83wVm8VAM4lWump poWSB6BBYXsuCdczCFMWaxDkBmmPCESEeLeZE09Y/swq3IDCAMMq3Dc98bflWvDS3w XA8ITqm00WrFpJ4iW+Yhi0FWbaX2I+Gzz38YYWyKEQ96bpW4TGC0kvdm8QtxImZwcJ IQXcPbq57ZB/GGYvRAXWwxDhbVgvNQI1KTikfqjIiHvlkhpPWJIQWvzbIbJBp8ryV2 X6V+BG6GYkvBZgaXy/CfVhwj1hmKi5b51DWWQfMLgh7gcDO4K8ShUuZZSD0yt2XII2 pf2D9+RsHl9Ng== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0DCD6C35FFF; Fri, 21 Mar 2025 12:14:46 +0000 (UTC) Date: Fri, 21 Mar 2025 16:14:41 +0400 Subject: [PATCH v6 3/6] dt-bindings: PCI: qcom: Add IPQ5018 SoC Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250321-ipq5018-pcie-v6-3-b7d659a76205@outlook.com> References: <20250321-ipq5018-pcie-v6-0-b7d659a76205@outlook.com> In-Reply-To: <20250321-ipq5018-pcie-v6-0-b7d659a76205@outlook.com> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nitheesh Sekar , Varadarajan Narayanan , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, George Moussalem , 20250317100029.881286-2-quic_varada@quicinc.com, Sricharan Ramabadhran X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1742559282; l=3072; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=n1pq98OF6nCyGBtv37e9qjebYlzLP26UOUQF23Nah7k=; b=QcJqr+eg1uuWXDOVJ3X4bfRhejU+SaW69uhV608YjWAsVsg5TKNFPFHIab3cdz/5ni+fJ1/Sy e8CuCbLSlo4CYMW1arxo5R4MDSM8REJlG3riZZgy6sm5HtIsw5IQjHS X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem From: Nitheesh Sekar Add support for the PCIe controller on the Qualcomm IPQ5108 SoC to the bindings. Signed-off-by: Nitheesh Sekar Signed-off-by: Sricharan Ramabadhran Signed-off-by: George Moussalem Reviewed-by: Krzysztof Kozlowski Acked-by: Manivannan Sadhasivam --- .../devicetree/bindings/pci/qcom,pcie.yaml | 50 ++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 469b99fa0f0e..668ff03f2561 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -21,6 +21,7 @@ properties: - qcom,pcie-apq8064 - qcom,pcie-apq8084 - qcom,pcie-ipq4019 + - qcom,pcie-ipq5018 - qcom,pcie-ipq6018 - qcom,pcie-ipq8064 - qcom,pcie-ipq8064-v2 @@ -168,6 +169,7 @@ allOf: compatible: contains: enum: + - qcom,pcie-ipq5018 - qcom,pcie-ipq6018 - qcom,pcie-ipq8074-gen3 - qcom,pcie-ipq9574 @@ -324,6 +326,53 @@ allOf: - const: ahb # AHB reset - const: phy_ahb # PHY AHB reset + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-ipq5018 + then: + properties: + clocks: + minItems: 6 + maxItems: 6 + clock-names: + items: + - const: iface # PCIe to SysNOC BIU clock + - const: axi_m # AXI Master clock + - const: axi_s # AXI Slave clock + - const: ahb # AHB clock + - const: aux # Auxiliary clock + - const: axi_bridge # AXI bridge clock + resets: + minItems: 8 + maxItems: 8 + reset-names: + items: + - const: pipe # PIPE reset + - const: sleep # Sleep reset + - const: sticky # Core sticky reset + - const: axi_m # AXI master reset + - const: axi_s # AXI slave reset + - const: ahb # AHB reset + - const: axi_m_sticky # AXI master sticky reset + - const: axi_s_sticky # AXI slave sticky reset + interrupts: + minItems: 9 + maxItems: 9 + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + - const: global + - if: properties: compatible: @@ -564,6 +613,7 @@ allOf: enum: - qcom,pcie-apq8064 - qcom,pcie-ipq4019 + - qcom,pcie-ipq5018 - qcom,pcie-ipq8064 - qcom,pcie-ipq8064v2 - qcom,pcie-ipq8074