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client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C Received: from SATLEXMB03.amd.com (165.204.84.17) by SJ1PEPF000023CF.mail.protection.outlook.com (10.167.244.11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8534.20 via Frontend Transport; Wed, 26 Mar 2025 02:29:08 +0000 Received: from SATLEXMB05.amd.com (10.181.40.146) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 25 Mar 2025 21:29:07 -0500 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB05.amd.com (10.181.40.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 25 Mar 2025 21:29:07 -0500 Received: from xhdlc200235.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.39 via Frontend Transport; Tue, 25 Mar 2025 21:29:03 -0500 From: Sai Krishna Musham To: , , , , , , , CC: , , , , , , Subject: [PATCH v6 1/2] dt-bindings: PCI: xilinx-cpm: Add reset-gpios for PCIe RP PERST# Date: Wed, 26 Mar 2025 07:58:10 +0530 Message-ID: <20250326022811.3090688-2-sai.krishna.musham@amd.com> X-Mailer: git-send-email 2.44.1 In-Reply-To: <20250326022811.3090688-1-sai.krishna.musham@amd.com> References: <20250326022811.3090688-1-sai.krishna.musham@amd.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Received-SPF: None (SATLEXMB05.amd.com: sai.krishna.musham@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023CF:EE_|PH0PR12MB7096:EE_ X-MS-Office365-Filtering-Correlation-Id: 2a3ae992-9973-4356-a68a-08dd6c0dfcbc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|82310400026|1800799024|36860700013|376014; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Mar 2025 02:29:08.5668 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2a3ae992-9973-4356-a68a-08dd6c0dfcbc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023CF.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB7096 Introduce `reset-gpios` property to enable GPIO-based control of the PCIe RP PERST# signal, generating assert and deassert signals. Traditionally, the reset was managed in hardware and enabled during initialization. With this patch set, the reset will be handled by the driver. Consequently, the `reset-gpios` property must be explicitly provided to ensure proper functionality. Add CPM clock and reset control registers base (`cpm_crx`) to handle PCIe IP reset along with PCIe RP PERST# to avoid Link Training errors. Signed-off-by: Sai Krishna Musham --- Changes for v6: - Resolve ABI break. - Update commit message. Changes for v5: - Remove `reset-gpios` property from required as it is already present in pci-bus-common.yaml - Update commit message Changes for v4: - Add CPM clock and reset control registers base to handle PCIe IP reset. - Update commit message. Changes for v3: - None Changes for v2: - Add define from include/dt-bindings/gpio/gpio.h for PERST# polarity - Update commit message --- .../bindings/pci/xilinx-versal-cpm.yaml | 72 ++++++++++++++----- 1 file changed, 55 insertions(+), 17 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml index d674a24c8ccc..26e9cea41889 100644 --- a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml +++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml @@ -9,9 +9,6 @@ title: CPM Host Controller device tree for Xilinx Versal SoCs maintainers: - Bharat Kumar Gogada -allOf: - - $ref: /schemas/pci/pci-host-bridge.yaml# - properties: compatible: enum: @@ -21,18 +18,12 @@ properties: - xlnx,versal-cpm5nc-host reg: - items: - - description: CPM system level control and status registers. - - description: Configuration space region and bridge registers. - - description: CPM5 control and status registers. - minItems: 2 + minItems: 3 + maxItems: 4 reg-names: - items: - - const: cpm_slcr - - const: cfg - - const: cpm_csr - minItems: 2 + minItems: 3 + maxItems: 4 interrupts: maxItems: 1 @@ -72,10 +63,53 @@ required: - msi-map - interrupt-controller +allOf: + - $ref: /schemas/pci/pci-host-bridge.yaml# + - if: + properties: + compatible: + contains: + enum: + - xlnx,versal-cpm-host-1.00 + then: + properties: + reg: + items: + - description: CPM system level control and status registers. + - description: Configuration space region and bridge registers. + - description: CPM clock and reset control registers. + reg-names: + items: + - const: cpm_slcr + - const: cfg + - const: cpm_crx + - if: + properties: + compatible: + contains: + enum: + - xlnx,versal-cpm5-host + - xlnx,versal-cpm5-host1 + then: + properties: + reg: + items: + - description: CPM system level control and status registers. + - description: Configuration space region and bridge registers. + - description: CPM5 control and status registers. + - description: CPM clock and reset control registers. + reg-names: + items: + - const: cpm_slcr + - const: cfg + - const: cpm_csr + - const: cpm_crx + unevaluatedProperties: false examples: - | + #include versal { #address-cells = <2>; @@ -98,8 +132,10 @@ examples: <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>; msi-map = <0x0 &its_gic 0x0 0x10000>; reg = <0x0 0xfca10000 0x0 0x1000>, - <0x6 0x00000000 0x0 0x10000000>; - reg-names = "cpm_slcr", "cfg"; + <0x6 0x00000000 0x0 0x10000000>, + <0x0 0xfca00000 0x0 10000>; + reg-names = "cpm_slcr", "cfg", "cpm_crx"; + reset-gpios = <&gpio1 38 GPIO_ACTIVE_LOW>; pcie_intc_0: interrupt-controller { #address-cells = <0>; #interrupt-cells = <1>; @@ -126,8 +162,10 @@ examples: msi-map = <0x0 &its_gic 0x0 0x10000>; reg = <0x00 0xfcdd0000 0x00 0x1000>, <0x06 0x00000000 0x00 0x1000000>, - <0x00 0xfce20000 0x00 0x1000000>; - reg-names = "cpm_slcr", "cfg", "cpm_csr"; + <0x00 0xfce20000 0x00 0x1000000>, + <0x00 0xfcdc0000 0x00 0x10000>; + reg-names = "cpm_slcr", "cfg", "cpm_csr", "cpm_crx"; + reset-gpios = <&gpio1 38 GPIO_ACTIVE_LOW>; pcie_intc_1: interrupt-controller { #address-cells = <0>;