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Fri, 11 Apr 2025 18:36:58 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, manivannan.sadhasivam@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manikandan K Pillai , Hans Zhang Subject: [PATCH v3 6/6] PCI: cadence: Update support for TI J721e boards Date: Fri, 11 Apr 2025 18:36:56 +0800 Message-ID: <20250411103656.2740517-7-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250411103656.2740517-1-hans.zhang@cixtech.com> References: <20250411103656.2740517-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TY2PEPF0000AB85:EE_|TYSPR06MB6972:EE_ X-MS-Office365-Filtering-Correlation-Id: 0defa126-df32-4e66-c610-08dd78e4cc48 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|376014|1800799024; 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X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Apr 2025 10:37:02.8862 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0defa126-df32-4e66-c610-08dd78e4cc48 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: TY2PEPF0000AB85.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: TYSPR06MB6972 From: Manikandan K Pillai Update the support for TI J721 boards to use the updated Cadence PCIe controller code. Signed-off-by: Manikandan K Pillai Signed-off-by: Hans Zhang --- drivers/pci/controller/cadence/pci-j721e.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c index ef1cfdae33bb..154b36c30101 100644 --- a/drivers/pci/controller/cadence/pci-j721e.c +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -164,6 +164,14 @@ static const struct cdns_pcie_ops j721e_pcie_ops = { .start_link = j721e_pcie_start_link, .stop_link = j721e_pcie_stop_link, .link_up = j721e_pcie_link_up, + .host_init_root_port = cdns_pcie_host_init_root_port, + .host_bar_ib_config = cdns_pcie_host_bar_ib_config, + .host_init_address_translation = cdns_pcie_host_init_address_translation, + .detect_quiet_min_delay_set = cdns_pcie_detect_quiet_min_delay_set, + .set_outbound_region = cdns_pcie_set_outbound_region, + .set_outbound_region_for_normal_msg = + cdns_pcie_set_outbound_region_for_normal_msg, + .reset_outbound_region = cdns_pcie_reset_outbound_region, }; static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *syscon, @@ -479,6 +487,8 @@ static int j721e_pcie_probe(struct platform_device *pdev) cdns_pcie = &rc->pcie; cdns_pcie->dev = dev; + cdns_pcie->is_rc = true; + cdns_pcie->is_hpa = false; cdns_pcie->ops = &j721e_pcie_ops; pcie->cdns_pcie = cdns_pcie; break; @@ -495,6 +505,8 @@ static int j721e_pcie_probe(struct platform_device *pdev) cdns_pcie = &ep->pcie; cdns_pcie->dev = dev; + cdns_pcie->is_rc = false; + cdns_pcie->is_hpa = false; cdns_pcie->ops = &j721e_pcie_ops; pcie->cdns_pcie = cdns_pcie; break;