From patchwork Fri May 29 18:24:29 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Duc Dang X-Patchwork-Id: 6510481 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id BA60B9F1C1 for ; Fri, 29 May 2015 18:25:41 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C85602055D for ; Fri, 29 May 2015 18:25:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3D84E20811 for ; Fri, 29 May 2015 18:25:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756725AbbE2SZg (ORCPT ); Fri, 29 May 2015 14:25:36 -0400 Received: from exprod5og120.obsmtp.com ([64.18.0.137]:55150 "EHLO mail-pd0-f172.google.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1756513AbbE2SZR (ORCPT ); Fri, 29 May 2015 14:25:17 -0400 Received: from mail-pd0-f172.google.com ([209.85.192.172]) (using TLSv1) by exprod5ob120.postini.com ([64.18.4.12]) with SMTP ID DSNKVWivDQCAk4A4LPF2D2iabyq1kc325aHC@postini.com; Fri, 29 May 2015 11:25:17 PDT Received: by pdbki1 with SMTP id ki1so59271238pdb.1 for ; Fri, 29 May 2015 11:25:16 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=1BD7wtjks+a6BD2lS4ao83EJkfOBTehA8pmGXo7X1Q8=; b=UODGG7xDvetQvE+sG6YquDC5JGGUNWrp2wU7R0XxVyWSyPhBEydXR3R3UlVNlC9k4t Y0JzxskCrR45aYT90M/xsBk59wYuA/ujPYA/FU3u3nu8kTOsx9Y+d5MvDspr3BMvmTb8 gB19eSIHdXWdA2nHx5vJGb+/ywVeYdzKvh1dJ4uAsARLPAaQ2a3gbuUx7OXtU67KS4Fd 2tNoqNkC8vGNodocdrPTXmIRzPgvStNB0Q6IyKSpjG3ZJz85B88c3EUowNBBjdcHGDdk ejGwOiZYY0+O3CvqJ+YKEHXytYrH+qeWQi0DwidgKMrS22ZsicUyhZX5geh094czwryM cQxA== X-Gm-Message-State: ALoCoQlLcI0ycD6fGGQi20x5Rqs0VF94RA/e8uUybZSRuhuUZdDeSYsEsRa2kLSD/Uk7j1pc/O/Re9UBBELwg1rk45NU7hPq+bkVD+3n+O5vhCAo4CxCwcYPRFECnjifPJTtmJR9b8gtRxOG1Aww3iv7egjEi7s7yw== X-Received: by 10.66.120.176 with SMTP id ld16mr17218442pab.17.1432923916899; Fri, 29 May 2015 11:25:16 -0700 (PDT) X-Received: by 10.66.120.176 with SMTP id ld16mr17218422pab.17.1432923916805; Fri, 29 May 2015 11:25:16 -0700 (PDT) Received: from dhdang-Precision-WorkStation-T3400.amcc.com (67-207-112-226.static.wiline.com. [67.207.112.226]) by mx.google.com with ESMTPSA id ml6sm6278602pdb.69.2015.05.29.11.25.15 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 29 May 2015 11:25:16 -0700 (PDT) From: Duc Dang To: Bjorn Helgaas , Arnd Bergmann , Grant Likely , Liviu Dudau , Marc Zyngier , Thomas Gleixner , Jason Cooper , Mark Rutland Cc: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Tanmay Inamdar , Loc Ho , Feng Kan , Duc Dang Subject: [PATCH v10 1/4] documentation: dts: Add the device tree binding for APM X-Gene v1 PCIe MSI device tree node Date: Fri, 29 May 2015 11:24:29 -0700 Message-Id: <2e6071ac3c663cee95e29d5c4606d049692ca9c2.1432922451.git.dhdang@apm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: References: In-Reply-To: References: <5566CC58.8080400@arm.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP X-Gene v1 PCIe MSI controller block provides PCIE MSI functionality for 5 X-Gene v1 PCIE ports The driver for this binding is under 'drivers/pci/host/pci-xgene-msi.c' Signed-off-by: Duc Dang Signed-off-by: Tanmay Inamdar Reviewed-by: Marc Zyngier --- .../devicetree/bindings/pci/xgene-pci-msi.txt | 68 ++++++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/xgene-pci-msi.txt diff --git a/Documentation/devicetree/bindings/pci/xgene-pci-msi.txt b/Documentation/devicetree/bindings/pci/xgene-pci-msi.txt new file mode 100644 index 0000000..36d881c --- /dev/null +++ b/Documentation/devicetree/bindings/pci/xgene-pci-msi.txt @@ -0,0 +1,68 @@ +* AppliedMicro X-Gene v1 PCIe MSI controller + +Required properties: + +- compatible: should be "apm,xgene1-msi" to identify + X-Gene v1 PCIe MSI controller block. +- msi-controller: indicates that this is X-Gene v1 PCIe MSI controller node +- reg: physical base address (0x79000000) and length (0x900000) for controller + registers. These registers include the MSI termination address and data + registers as well as the MSI interrupt status registers. +- reg-names: not required +- interrupts: A list of 16 interrupt outputs of the controller, starting from + interrupt number 0x10 to 0x1f. +- interrupt-names: not required + +Each PCIe node needs to have property msi-parent that points to msi controller node + +Examples: + +SoC DTSI: + + + MSI node: + msi@79000000 { + compatible = "apm,xgene1-msi"; + msi-controller; + reg = <0x00 0x79000000 0x0 0x900000>; + interrupts = <0x0 0x10 0x4> + <0x0 0x11 0x4> + <0x0 0x12 0x4> + <0x0 0x13 0x4> + <0x0 0x14 0x4> + <0x0 0x15 0x4> + <0x0 0x16 0x4> + <0x0 0x17 0x4> + <0x0 0x18 0x4> + <0x0 0x19 0x4> + <0x0 0x1a 0x4> + <0x0 0x1b 0x4> + <0x0 0x1c 0x4> + <0x0 0x1d 0x4> + <0x0 0x1e 0x4> + <0x0 0x1f 0x4>; + }; + + + PCIe controller node with msi-parent property pointing to MSI node: + pcie0: pcie@1f2b0000 { + status = "disabled"; + device_type = "pci"; + compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */ + 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */ + reg-names = "csr", "cfg"; + ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */ + 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */ + dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 + 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1 + 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1 + 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1 + 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>; + dma-coherent; + clocks = <&pcie0clk 0>; + msi-parent= <&msi>; + };