From patchwork Wed Jun 10 09:08:15 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Allen Hubbe X-Patchwork-Id: 6580751 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 84176C0020 for ; Wed, 10 Jun 2015 14:14:07 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7A54B20497 for ; Wed, 10 Jun 2015 14:14:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3065D205C1 for ; Wed, 10 Jun 2015 14:14:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754196AbbFJONv (ORCPT ); Wed, 10 Jun 2015 10:13:51 -0400 Received: from mailuogwhop.emc.com ([168.159.213.141]:46388 "EHLO mailuogwhop.emc.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965295AbbFJOJI (ORCPT ); Wed, 10 Jun 2015 10:09:08 -0400 Received: from maildlpprd06.lss.emc.com (maildlpprd06.lss.emc.com [10.253.24.38]) by mailuogwprd03.lss.emc.com (Sentrion-MTA-4.3.1/Sentrion-MTA-4.3.0) with ESMTP id t5AE92w7008093 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Wed, 10 Jun 2015 10:09:05 -0400 X-DKIM: OpenDKIM Filter v2.4.3 mailuogwprd03.lss.emc.com t5AE92w7008093 DKIM-Signature: v=1; a=rsa-sha1; c=relaxed/relaxed; d=emc.com; s=jan2013; t=1433945345; bh=/oVSKyL+3LLm1wzv1x+Lu7lXIMI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: In-Reply-To:References; b=OEqBxTtVkwX7EB5HEWHBvYSfhrzgsGib2EzFQ4xrT1KgjkX0fCQK5ZgPu0/u1ZQoU TE+s3+QheqLFthnmFurQcTAAPQMT46vJzkNU8+Ksg/ZwjGh50G27zHYXP2BBU8yNXl YOZQ/Gao+i9CgL9QWTzYHGZ7PCY/ikyZIZTJVRIQ= X-DKIM: OpenDKIM Filter v2.4.3 mailuogwprd03.lss.emc.com t5AE92w7008093 Received: from mailsyshubprd56.lss.emc.com (mailhub.lss.emc.com [10.106.48.138]) by maildlpprd06.lss.emc.com (RSA Interceptor); Wed, 10 Jun 2015 10:08:51 -0400 Received: from HY-R1012-SPA.usd.lab.emc.com.com (hy-r1012-spa.rtp.lab.emc.com [10.6.71.221]) by mailsyshubprd56.lss.emc.com (Sentrion-MTA-4.3.1/Sentrion-MTA-4.3.0) with ESMTP id t5AE8iKS021690; Wed, 10 Jun 2015 10:08:52 -0400 From: Allen Hubbe To: linux-ntb@googlegroups.com Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Jon Mason , Dave Jiang , Allen Hubbe Subject: [PATCH v4 10/19] NTB: Add parameters for Intel SNB B2B addresses Date: Wed, 10 Jun 2015 05:08:15 -0400 Message-Id: <3a9a0aa9066748dcaf21da955ac6361ca3b6d280.1433925092.git.Allen.Hubbe@emc.com> X-Mailer: git-send-email 2.4.0.rc0.44.g244209c.dirty In-Reply-To: References: In-Reply-To: References: X-RSA-Classifications: Source Code, public X-Sentrion-Hostname: mailuogwprd03.lss.emc.com Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-5.2 required=5.0 tests=BAYES_00, DATE_IN_PAST_03_06, DKIM_SIGNED,RCVD_IN_DNSWL_HI,T_DKIM_INVALID,T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add module parameters for the addresses to be used in B2B topology. Signed-off-by: Allen Hubbe --- Documentation/ntb.txt | 10 +++++ drivers/ntb/hw/intel/ntb_hw_intel.c | 77 ++++++++++++++++++++++++++++--------- 2 files changed, 68 insertions(+), 19 deletions(-) diff --git a/Documentation/ntb.txt b/Documentation/ntb.txt index 725ba1e6c127..00a3f92832a5 100644 --- a/Documentation/ntb.txt +++ b/Documentation/ntb.txt @@ -56,3 +56,13 @@ Module Parameters: * b2b\_mw\_share - If the peer ntb is to be accessed via a memory window, and if the memory window is large enough, still allow the client to use the second half of the memory window for address translation to the peer. +* snb\_b2b\_usd\_bar2\_addr64 - If using B2B topology on Xeon hardware, use this + 64 bit address on the bus between the NTB devices for the window at + BAR2, on the upstream side of the link. +* snb\_b2b\_usd\_bar4\_addr64 - See *snb\_b2b\_bar2\_addr64*. +* snb\_b2b\_usd\_bar4\_addr32 - See *snb\_b2b\_bar2\_addr64*. +* snb\_b2b\_usd\_bar5\_addr32 - See *snb\_b2b\_bar2\_addr64*. +* snb\_b2b\_dsd\_bar2\_addr64 - See *snb\_b2b\_bar2\_addr64*. +* snb\_b2b\_dsd\_bar4\_addr64 - See *snb\_b2b\_bar2\_addr64*. +* snb\_b2b\_dsd\_bar4\_addr32 - See *snb\_b2b\_bar2\_addr64*. +* snb\_b2b\_dsd\_bar5\_addr32 - See *snb\_b2b\_bar2\_addr64*. diff --git a/drivers/ntb/hw/intel/ntb_hw_intel.c b/drivers/ntb/hw/intel/ntb_hw_intel.c index ff397fae9cf4..3448d5fbd003 100644 --- a/drivers/ntb/hw/intel/ntb_hw_intel.c +++ b/drivers/ntb/hw/intel/ntb_hw_intel.c @@ -72,20 +72,6 @@ MODULE_AUTHOR("Intel Corporation"); #define bar0_off(base, bar) ((base) + ((bar) << 2)) #define bar2_off(base, bar) bar0_off(base, (bar) - 2) -static int b2b_mw_idx = -1; -module_param(b2b_mw_idx, int, 0644); -MODULE_PARM_DESC(b2b_mw_idx, "Use this mw idx to access the peer ntb. A " - "value of zero or positive starts from first mw idx, and a " - "negative value starts from last mw idx. Both sides MUST " - "set the same value here!"); - -static unsigned int b2b_mw_share; -module_param(b2b_mw_share, uint, 0644); -MODULE_PARM_DESC(b2b_mw_share, "If the b2b mw is large enough, configure the " - "ntb so that the peer ntb only occupies the first half of " - "the mw, so the second half can still be used as a mw. Both " - "sides MUST set the same value here!"); - static const struct intel_ntb_reg bwd_reg; static const struct intel_ntb_alt_reg bwd_pri_reg; static const struct intel_ntb_alt_reg bwd_sec_reg; @@ -98,14 +84,67 @@ static const struct intel_ntb_alt_reg snb_sec_reg; static const struct intel_ntb_alt_reg snb_b2b_reg; static const struct intel_ntb_xlat_reg snb_pri_xlat; static const struct intel_ntb_xlat_reg snb_sec_xlat; -static const struct intel_b2b_addr snb_b2b_usd_addr; -static const struct intel_b2b_addr snb_b2b_dsd_addr; - +static struct intel_b2b_addr snb_b2b_usd_addr; +static struct intel_b2b_addr snb_b2b_dsd_addr; static const struct ntb_dev_ops intel_ntb_ops; static const struct file_operations intel_ntb_debugfs_info; static struct dentry *debugfs_dir; +static int b2b_mw_idx = -1; +module_param(b2b_mw_idx, int, 0644); +MODULE_PARM_DESC(b2b_mw_idx, "Use this mw idx to access the peer ntb. A " + "value of zero or positive starts from first mw idx, and a " + "negative value starts from last mw idx. Both sides MUST " + "set the same value here!"); + +static unsigned int b2b_mw_share; +module_param(b2b_mw_share, uint, 0644); +MODULE_PARM_DESC(b2b_mw_share, "If the b2b mw is large enough, configure the " + "ntb so that the peer ntb only occupies the first half of " + "the mw, so the second half can still be used as a mw. Both " + "sides MUST set the same value here!"); + +module_param_named(snb_b2b_usd_bar2_addr64, + snb_b2b_usd_addr.bar2_addr64, ullong, 0644); +MODULE_PARM_DESC(snb_b2b_usd_bar2_addr64, + "SNB B2B USD BAR 2 64-bit address"); + +module_param_named(snb_b2b_usd_bar4_addr64, + snb_b2b_usd_addr.bar4_addr64, ullong, 0644); +MODULE_PARM_DESC(snb_b2b_usd_bar2_addr64, + "SNB B2B USD BAR 4 64-bit address"); + +module_param_named(snb_b2b_usd_bar4_addr32, + snb_b2b_usd_addr.bar4_addr32, ullong, 0644); +MODULE_PARM_DESC(snb_b2b_usd_bar2_addr64, + "SNB B2B USD split-BAR 4 32-bit address"); + +module_param_named(snb_b2b_usd_bar5_addr32, + snb_b2b_usd_addr.bar5_addr32, ullong, 0644); +MODULE_PARM_DESC(snb_b2b_usd_bar2_addr64, + "SNB B2B USD split-BAR 5 32-bit address"); + +module_param_named(snb_b2b_dsd_bar2_addr64, + snb_b2b_dsd_addr.bar2_addr64, ullong, 0644); +MODULE_PARM_DESC(snb_b2b_dsd_bar2_addr64, + "SNB B2B DSD BAR 2 64-bit address"); + +module_param_named(snb_b2b_dsd_bar4_addr64, + snb_b2b_dsd_addr.bar4_addr64, ullong, 0644); +MODULE_PARM_DESC(snb_b2b_dsd_bar2_addr64, + "SNB B2B DSD BAR 4 64-bit address"); + +module_param_named(snb_b2b_dsd_bar4_addr32, + snb_b2b_dsd_addr.bar4_addr32, ullong, 0644); +MODULE_PARM_DESC(snb_b2b_dsd_bar2_addr64, + "SNB B2B DSD split-BAR 4 32-bit address"); + +module_param_named(snb_b2b_dsd_bar5_addr32, + snb_b2b_dsd_addr.bar5_addr32, ullong, 0644); +MODULE_PARM_DESC(snb_b2b_dsd_bar2_addr64, + "SNB B2B DSD split-BAR 5 32-bit address"); + #ifndef ioread64 #ifdef readq #define ioread64 readq @@ -2078,14 +2117,14 @@ static const struct intel_ntb_xlat_reg snb_sec_xlat = { .bar2_xlat = SNB_SBAR23XLAT_OFFSET, }; -static const struct intel_b2b_addr snb_b2b_usd_addr = { +static struct intel_b2b_addr snb_b2b_usd_addr = { .bar2_addr64 = SNB_B2B_BAR2_USD_ADDR64, .bar4_addr64 = SNB_B2B_BAR4_USD_ADDR64, .bar4_addr32 = SNB_B2B_BAR4_USD_ADDR32, .bar5_addr32 = SNB_B2B_BAR5_USD_ADDR32, }; -static const struct intel_b2b_addr snb_b2b_dsd_addr = { +static struct intel_b2b_addr snb_b2b_dsd_addr = { .bar2_addr64 = SNB_B2B_BAR2_DSD_ADDR64, .bar4_addr64 = SNB_B2B_BAR4_DSD_ADDR64, .bar4_addr32 = SNB_B2B_BAR4_DSD_ADDR32,