From patchwork Fri Jul 21 02:32:47 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Honghui Zhang X-Patchwork-Id: 9855923 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D3494600F5 for ; Fri, 21 Jul 2017 02:34:48 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BFC42286C4 for ; Fri, 21 Jul 2017 02:34:48 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B46D7286DD; Fri, 21 Jul 2017 02:34:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1717B286C4 for ; Fri, 21 Jul 2017 02:34:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S966087AbdGUCeL (ORCPT ); Thu, 20 Jul 2017 22:34:11 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:25859 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S966260AbdGUCdD (ORCPT ); Thu, 20 Jul 2017 22:33:03 -0400 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 776274300; Fri, 21 Jul 2017 10:32:57 +0800 Received: from mtkexhb01.mediatek.inc (172.21.101.102) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Fri, 21 Jul 2017 10:32:56 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkexhb01.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Fri, 21 Jul 2017 10:32:56 +0800 From: To: , , , , , , , , , , CC: , , , , , , Subject: [PATCH 5/5] dt-bindings: PCI: add support for new generation controller Date: Fri, 21 Jul 2017 10:32:47 +0800 Message-ID: <3b449a88bd2f57ee005674d0161192ee01167e5a.1500601172.git.honghui.zhang@mediatek.com> X-Mailer: git-send-email 2.6.4 In-Reply-To: References: MIME-Version: 1.0 X-MTK: N Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Ryder Lee Add support for MediaTek new generation controller and update related properities. Signed-off-by: Ryder Lee Signed-off-by: Honghui Zhang --- .../devicetree/bindings/pci/mediatek-pcie.txt | 84 ++++++++++++++++++++-- 1 file changed, 79 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt index 294f4a3..a1f3767 100644 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt @@ -4,17 +4,27 @@ Required properties: - compatible: Should contain one of the following string: "mediatek,mt7623-pcie" "mediatek,mt2701-pcie" + "mediatek,generic-pcie-v2" - device_type: Must be "pci" -- reg: Base addresses and lengths of the PCIe controller. +- reg: Base addresses and lengths of the PICe subsys and root ports. +- reg-names: Names of the above areas to use during resource look-up. - #address-cells: Address representation for root ports (must be 3) - #size-cells: Size representation for root ports (must be 2) - clocks: Must contain an entry for each entry in clock-names. See ../clocks/clock-bindings.txt for details. - clock-names: Must include the following entries: - free_ck :for reference clock of PCIe subsys - - sys_ck0 :for clock of Port0 - - sys_ck1 :for clock of Port1 - - sys_ck2 :for clock of Port2 + - sys_ckN :transaction layer and data link layer clock + The "sys_ck" might be divided into the following parts in some v2 chips: + - ahb_ckN :AHB slave interface operating clock for CSR access and RC + initiated MMIO access + - axi_ckN :application layer MMIO channel operating clock + - aux_ckN :pe2_mac_bridge and pe2_mac_core operating clock when + pcie_mac_ck/pcie_pipe_ck is turned off + - obff_ckN :OBFF functional block operating clock + - pipe_ckN :pe2_mac_bridge and pe2_mac_core operating clock when + pcie_mac_ck/pcie_pipe_ck is turned off + where N starting from 0 to the maximum number of root ports. - phys: List of PHY specifiers (used by generic PHY framework). - phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the number of PHYs as specified in *phys* property. @@ -33,6 +43,9 @@ Required properties for MT7623/MT2701: - reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the number of root ports. +Required properties for mediatek generic-pcie-v2: +-interrupts: A list of interrupt outputs of the controller. + In addition, the device tree node must have sub-nodes describing each PCIe port interface, having the following mandatory properties: @@ -50,7 +63,7 @@ Required properties: property is sufficient. - num-lanes: Number of lanes to use for this port. -Examples: +Examples for mt7623: hifsys: syscon@1a000000 { compatible = "mediatek,mt7623-hifsys", @@ -68,6 +81,7 @@ Examples: <0 0x1a142000 0 0x1000>, /* Port0 registers */ <0 0x1a143000 0 0x1000>, /* Port1 registers */ <0 0x1a144000 0 0x1000>; /* Port2 registers */ + reg-names = "subsys", "port0", "port1", "port2"; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; @@ -127,3 +141,63 @@ Examples: num-lanes = <1>; }; }; + +Examples for mt2712: + pcie: pcie@0x11700000 { + compatible = "mediatek,generic-pcie-v2"; + device_type = "pci"; + reg = <0 0x11700000 0 0x1000>, + <0 0x112FF000 0 0x1000>; + reg-names = "port0", "port1"; + #address-cells = <3>; + #size-cells = <2>; + interrupts = , + ; + clocks = <&pericfg CLK_PERI_PCIE0>, + <&pericfg CLK_PERI_PCIE1>, + <&topckgen CLK_TOP_PE2_MAC_P0_SEL>, + <&topckgen CLK_TOP_PE2_MAC_P1_SEL>; + clock-names = "sys_ck0", "sys_ck1", "ahb0", "ahb1"; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; + + pcie0: pcie@0,0 { + device_type = "pci"; + reg = <0x0000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + num-lanes = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc0 0>, + <0 0 0 2 &pcie_intc0 1>, + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + pcie_intc0: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + + pcie1: pcie@1,0 { + device_type = "pci"; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + num-lanes = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc1 0>, + <0 0 0 2 &pcie_intc1 1>, + <0 0 0 3 &pcie_intc1 2>, + <0 0 0 4 &pcie_intc1 3>; + pcie_intc1: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + };