From patchwork Wed May 13 03:19:00 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kenji Kaneshige X-Patchwork-Id: 23473 Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id n4D3KaYV018614 for ; Wed, 13 May 2009 03:20:36 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760219AbZEMDTW (ORCPT ); Tue, 12 May 2009 23:19:22 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1760176AbZEMDTW (ORCPT ); Tue, 12 May 2009 23:19:22 -0400 Received: from fgwmail7.fujitsu.co.jp ([192.51.44.37]:49919 "EHLO fgwmail7.fujitsu.co.jp" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1760212AbZEMDTV (ORCPT ); Tue, 12 May 2009 23:19:21 -0400 Received: from m6.gw.fujitsu.co.jp ([10.0.50.76]) by fgwmail7.fujitsu.co.jp (Fujitsu Gateway) with ESMTP id n4D3JKV0009870 for (envelope-from kaneshige.kenji@jp.fujitsu.com); Wed, 13 May 2009 12:19:21 +0900 Received: from smail (m6 [127.0.0.1]) by outgoing.m6.gw.fujitsu.co.jp (Postfix) with ESMTP id B35B945DE51 for ; Wed, 13 May 2009 12:19:20 +0900 (JST) Received: from s6.gw.fujitsu.co.jp (s6.gw.fujitsu.co.jp [10.0.50.96]) by m6.gw.fujitsu.co.jp (Postfix) with ESMTP id 8AF4945DE55 for ; Wed, 13 May 2009 12:19:20 +0900 (JST) Received: from s6.gw.fujitsu.co.jp (localhost.localdomain [127.0.0.1]) by s6.gw.fujitsu.co.jp (Postfix) with ESMTP id 87E811DB8042 for ; Wed, 13 May 2009 12:19:20 +0900 (JST) Received: from m107.s.css.fujitsu.com (m107.s.css.fujitsu.com [10.249.87.107]) by s6.gw.fujitsu.co.jp (Postfix) with ESMTP id 25CEF1DB8038 for ; Wed, 13 May 2009 12:19:20 +0900 (JST) Received: from m107.css.fujitsu.com (m107 [127.0.0.1]) by m107.s.css.fujitsu.com (Postfix) with ESMTP id 8FAAE67000E; Wed, 13 May 2009 12:19:19 +0900 (JST) Received: from [127.0.0.1] (unknown [10.124.100.137]) by m107.s.css.fujitsu.com (Postfix) with ESMTP id 6923B67000C; Wed, 13 May 2009 12:19:18 +0900 (JST) Message-ID: <4A0A3C24.3010803@jp.fujitsu.com> Date: Wed, 13 May 2009 12:19:00 +0900 From: Kenji Kaneshige User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) MIME-Version: 1.0 To: "linux-pci@vger.kernel.org" , Jesse Barnes CC: "Zhang, Yanmin" , "Li, Shaohua" Subject: [PATCH 8/14] PCI ASPM: cleanup __pcie_aspm_check_state_one References: <4A0A3A24.5030501@jp.fujitsu.com> In-Reply-To: <4A0A3A24.5030501@jp.fujitsu.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Clean up and simplify __pcie_aspm_check_state_one(). Signed-off-by: Kenji Kaneshige --- drivers/pci/pcie/aspm.c | 67 +++++++++++++++++------------------------------- 1 file changed, 25 insertions(+), 42 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Index: 20090508/drivers/pci/pcie/aspm.c =================================================================== --- 20090508.orig/drivers/pci/pcie/aspm.c +++ 20090508/drivers/pci/pcie/aspm.c @@ -370,56 +370,39 @@ static void pcie_aspm_cap_init(struct pc } } -static unsigned int __pcie_aspm_check_state_one(struct pci_dev *pdev, - unsigned int state) +/** + * __pcie_aspm_check_state_one - check latency for endpoint device. + * @endpoint: pointer to the struct pci_dev of endpoint device + * + * TBD: The latency from the endpoint to root complex vary per switch's + * upstream link state above the device. Here we just do a simple check + * which assumes all links above the device can be in L1 state, that + * is we just consider the worst case. If switch's upstream link can't + * be put into L0S/L1, then our check is too strictly. + */ +static u32 __pcie_aspm_check_state_one(struct pci_dev *endpoint, u32 state) { - struct pci_dev *parent_dev, *tmp_dev; - unsigned int l1_latency = 0; - struct pcie_link_state *link_state; + u32 l1_switch_latency = 0; struct aspm_latency *acceptable; + struct pcie_link_state *link; - parent_dev = pdev->bus->self; - link_state = parent_dev->link_state; - state &= link_state->aspm_support; - if (state == 0) - return 0; - acceptable = &link_state->acceptable[PCI_FUNC(pdev->devfn)]; + link = endpoint->bus->self->link_state; + state &= link->aspm_support; + acceptable = &link->acceptable[PCI_FUNC(endpoint->devfn)]; - /* - * Check latency for endpoint device. - * TBD: The latency from the endpoint to root complex vary per - * switch's upstream link state above the device. Here we just do a - * simple check which assumes all links above the device can be in L1 - * state, that is we just consider the worst case. If switch's upstream - * link can't be put into L0S/L1, then our check is too strictly. - */ - tmp_dev = pdev; - while (state & (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1)) { - parent_dev = tmp_dev->bus->self; - link_state = parent_dev->link_state; + while (link && state) { if ((state & PCIE_LINK_STATE_L0S) && - (link_state->latency.l0s > acceptable->l0s)) + (link->latency.l0s > acceptable->l0s)) state &= ~PCIE_LINK_STATE_L0S; - if ((state & PCIE_LINK_STATE_L1) && - (link_state->latency.l1 + l1_latency > acceptable->l1)) + (link->latency.l1 + l1_switch_latency > acceptable->l1)) state &= ~PCIE_LINK_STATE_L1; - - if (!parent_dev->bus->self) /* parent_dev is a root port */ - break; - else { - /* - * parent_dev is the downstream port of a switch, make - * tmp_dev the upstream port of the switch - */ - tmp_dev = parent_dev->bus->self; - /* - * every switch on the path to root complex need 1 more - * microsecond for L1. Spec doesn't mention L0S. - */ - if (state & PCIE_LINK_STATE_L1) - l1_latency += 1000; - } + link = link->parent; + /* + * Every switch on the path to root complex need 1 + * more microsecond for L1. Spec doesn't mention L0s. + */ + l1_switch_latency += 1000; } return state; }