From patchwork Wed May 13 04:10:17 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hidetoshi Seto X-Patchwork-Id: 23485 Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id n4D4BG9k022083 for ; Wed, 13 May 2009 04:11:16 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750793AbZEMELO (ORCPT ); Wed, 13 May 2009 00:11:14 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1750890AbZEMELN (ORCPT ); Wed, 13 May 2009 00:11:13 -0400 Received: from fgwmail7.fujitsu.co.jp ([192.51.44.37]:51590 "EHLO fgwmail7.fujitsu.co.jp" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750793AbZEMELN (ORCPT ); Wed, 13 May 2009 00:11:13 -0400 Received: from m3.gw.fujitsu.co.jp ([10.0.50.73]) by fgwmail7.fujitsu.co.jp (Fujitsu Gateway) with ESMTP id n4D4BCTI030449 (envelope-from seto.hidetoshi@jp.fujitsu.com); Wed, 13 May 2009 13:11:12 +0900 Received: from smail (m3 [127.0.0.1]) by outgoing.m3.gw.fujitsu.co.jp (Postfix) with ESMTP id 008CB45DD7E; Wed, 13 May 2009 13:11:12 +0900 (JST) Received: from s3.gw.fujitsu.co.jp (s3.gw.fujitsu.co.jp [10.0.50.93]) by m3.gw.fujitsu.co.jp (Postfix) with ESMTP id D5C7145DD7D; Wed, 13 May 2009 13:11:11 +0900 (JST) Received: from s3.gw.fujitsu.co.jp (localhost.localdomain [127.0.0.1]) by s3.gw.fujitsu.co.jp (Postfix) with ESMTP id 9EBC1E08001; Wed, 13 May 2009 13:11:11 +0900 (JST) Received: from m107.s.css.fujitsu.com (m107.s.css.fujitsu.com [10.249.87.107]) by s3.gw.fujitsu.co.jp (Postfix) with ESMTP id 12CDA1DB8044; Wed, 13 May 2009 13:11:08 +0900 (JST) Received: from m107.css.fujitsu.com (m107 [127.0.0.1]) by m107.s.css.fujitsu.com (Postfix) with ESMTP id D67302C0107; Wed, 13 May 2009 13:11:07 +0900 (JST) Received: from [127.0.0.1] (unknown [10.124.100.141]) by m107.s.css.fujitsu.com (Postfix) with ESMTP id 58FBC2C00EE; Wed, 13 May 2009 13:11:07 +0900 (JST) Message-ID: <4A0A4829.8080709@jp.fujitsu.com> Date: Wed, 13 May 2009 13:10:17 +0900 From: Hidetoshi Seto User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) MIME-Version: 1.0 To: Matthew Wilcox , "David S. Miller" CC: Jesse Barnes , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH] PCI MSI: Yet another fix for MSI-X with NIU cards References: <20090508131333.GV8112@parisc-linux.org> In-Reply-To: <20090508131333.GV8112@parisc-linux.org> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Hi David, Could you review & test following patch for your issue? Thanks, H.Seto The NIU device refuses to allow accesses to MSI-X registers before MSI-X is enabled. This patch fixes the problem by removing the read & write of the mask register in msix_capability_init(). It will be safe since PCI spac says the maskbit's state after reset is always 1 (= masked). Reported-by: David S. Miller Signed-off-by: Hidetoshi Seto --- drivers/pci/msi.c | 4 +--- 1 files changed, 1 insertions(+), 3 deletions(-) diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c index 6f2e629..b680a5b 100644 --- a/drivers/pci/msi.c +++ b/drivers/pci/msi.c @@ -455,9 +455,7 @@ static int msix_capability_init(struct pci_dev *dev, entry->msi_attrib.default_irq = dev->irq; entry->msi_attrib.pos = pos; entry->mask_base = base; - entry->masked = readl(base + j * PCI_MSIX_ENTRY_SIZE + - PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET); - msix_mask_irq(entry, 1); + entry->masked = 1; list_add_tail(&entry->list, &dev->msi_list); }