From patchwork Sat Jul 4 05:09:36 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tejun Heo X-Patchwork-Id: 34039 Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id n6458wlJ013901 for ; Sat, 4 Jul 2009 05:08:58 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751386AbZGDFIG (ORCPT ); Sat, 4 Jul 2009 01:08:06 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1750816AbZGDFIG (ORCPT ); Sat, 4 Jul 2009 01:08:06 -0400 Received: from hera.kernel.org ([140.211.167.34]:39426 "EHLO hera.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751386AbZGDFIE (ORCPT ); Sat, 4 Jul 2009 01:08:04 -0400 Received: from htj.dyndns.org (IDENT:U2FsdGVkX1//RmYrHFO4NcpszXxDUcyiT5+alkeBOdY@localhost [127.0.0.1]) by hera.kernel.org (8.14.2/8.14.2) with ESMTP id n6457YGA009129 (version=TLSv1/SSLv3 cipher=DHE-RSA-CAMELLIA256-SHA bits=256 verify=NO); Sat, 4 Jul 2009 05:07:36 GMT Received: from [10.7.8.135] (a135.air [10.7.8.135]) by htj.dyndns.org (Postfix) with ESMTPSA id 50250406B28C6; Sat, 4 Jul 2009 14:07:34 +0900 (KST) Message-ID: <4A4EE410.4080001@kernel.org> Date: Sat, 04 Jul 2009 14:09:36 +0900 From: Tejun Heo User-Agent: Thunderbird 2.0.0.19 (X11/20081227) MIME-Version: 1.0 To: Greg KH , Robert Hancock , Alan Cox , linux-pci@vger.kernel.org, Linux Kernel , Daniel Ritz , Dominik Brodowski , Kenji Kaneshige , Axel Birndt , Benjamin Herrenschmidt , Ingo Molnar , Thomas Gleixner , Tony Luck , David Miller , Ingo Molnar Subject: [PATCH 2/3] pci,sparc64: drop PCI_CACHE_LINE_BYTES References: <4A4EE3E9.7090205@kernel.org> In-Reply-To: <4A4EE3E9.7090205@kernel.org> X-Enigmail-Version: 0.95.7 X-Virus-Scanned: ClamAV 0.93.3/9538/Fri Jul 3 14:27:11 2009 on hera.kernel.org X-Virus-Status: Clean X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00, UNPARSEABLE_RELAY autolearn=ham version=3.2.5 X-Spam-Checker-Version: SpamAssassin 3.2.5 (2008-06-10) on hera.kernel.org X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.0 (hera.kernel.org [127.0.0.1]); Sat, 04 Jul 2009 05:07:36 +0000 (UTC) Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org sparc64 is now the only user of PCI_CACHE_LINE_BYTES. Drop it and set pci_dfl_cache_line_size from pcibios_init() instead and drop PCI_CACHE_LINE_BYTES handling from generic pci code. Orignally-From: David Miller Signed-off-by: Tejun Heo --- arch/sparc/include/asm/pci_64.h | 2 -- arch/sparc/kernel/pci.c | 7 +++++++ drivers/pci/pci.c | 6 +----- 3 files changed, 8 insertions(+), 7 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Index: work/arch/sparc/kernel/pci.c =================================================================== --- work.orig/arch/sparc/kernel/pci.c +++ work/arch/sparc/kernel/pci.c @@ -1081,3 +1081,10 @@ void pci_resource_to_user(const struct p *start = rp->start - offset; *end = rp->end - offset; } + +static int __init pcibios_init(void) +{ + pci_dfl_cache_line_size = 64 >> 2; + return 0; +} +subsys_initcall(pcibios_init); Index: work/arch/sparc/include/asm/pci_64.h =================================================================== --- work.orig/arch/sparc/include/asm/pci_64.h +++ work/arch/sparc/include/asm/pci_64.h @@ -17,8 +17,6 @@ #define PCI_IRQ_NONE 0xffffffff -#define PCI_CACHE_LINE_BYTES 64 - static inline void pcibios_set_master(struct pci_dev *dev) { /* No special bus mastering setup handling */ Index: work/drivers/pci/pci.c =================================================================== --- work.orig/drivers/pci/pci.c +++ work/drivers/pci/pci.c @@ -41,17 +41,13 @@ int pci_domains_supported = 1; unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE; unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE; -#ifndef PCI_CACHE_LINE_BYTES -#define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES -#endif - /* * The default CLS is used if arch didn't set CLS explicitly and not * all pci devices agree on the same value. Arch can override either * the dfl or actual value as it sees fit. Don't forget this is * measured in 32-bit words, not bytes. */ -u8 pci_dfl_cache_line_size __initdata = PCI_CACHE_LINE_BYTES >> 2; +u8 pci_dfl_cache_line_size __initdata = L1_CACHE_BYTES >> 2; u8 pci_cache_line_size; /**