| Message ID | 4A7221DF.5040402@us.ibm.com (mailing list archive) |
|---|---|
| State | Accepted, archived |
| Headers | show |
2009/7/30 Mike Mason <mmlnx@us.ibm.com>: > This is the third of three patches that implement a bit field that PCI > Express device drivers can use to indicate they need a fundamental reset > during error recovery. > > By default, the EEH framework on powerpc does what's known as a "hot reset" > during recovery of a PCI Express device. Â We've found a case where the > device needs a "fundamental reset" to recover properly. Â The current PCI > error recovery and EEH frameworks do not support this distinction. > > The attached patch makes changes to EEH to utilize the new bit field. > > These patches supersede the previously submitted patch that implemented a > fundamental reset bit field. > > Please review and let me know of any concerns. > > Signed-off-by: Mike Mason <mmlnx@us.ibm.com> > Signed-off-by: Richard Lary <rlary@us.ibm.com> Signed-off-by: Linas Vepstas <linasvepstas@gmail.com> > + Â Â Â /* Determine type of EEH reset required by device, > + Â Â Â Â * default hot reset or fundamental reset > + Â Â Â Â */ > + Â Â Â if (dev->needs_freset) > + Â Â Â Â Â Â Â rtas_pci_slot_reset(pdn, 3); > + Â Â Â else > + Â Â Â Â Â Â Â rtas_pci_slot_reset(pdn, 1); Gack! I remember deluges of emails and conference calls where the hardware guys went on about this; and I admit I didn't quite get it, which I guess is why this patch is showing up many years late. FWIW some of the variants of the IPR chipset almost surely need the freset bit set. --linas -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff -uNrp a/arch/powerpc/kernel/pci_64.c b/arch/powerpc/kernel/pci_64.c --- a/arch/powerpc/kernel/pci_64.c 2009-07-13 14:25:24.000000000 -0700 +++ b/arch/powerpc/kernel/pci_64.c 2009-07-15 10:26:26.000000000 -0700 @@ -143,6 +143,7 @@ struct pci_dev *of_create_pci_dev(struct dev->dev.bus = &pci_bus_type; dev->devfn = devfn; dev->multifunction = 0; /* maybe a lie? */ + dev->needs_freset = 0; /* pcie fundamental reset required */ dev->vendor = get_int_prop(node, "vendor-id", 0xffff); dev->device = get_int_prop(node, "device-id", 0xffff); diff -uNrp a/arch/powerpc/platforms/pseries/eeh.c b/arch/powerpc/platforms/pseries/eeh.c --- a/arch/powerpc/platforms/pseries/eeh.c 2009-06-09 20:05:27.000000000 -0700 +++ b/arch/powerpc/platforms/pseries/eeh.c 2009-07-15 10:29:04.000000000 -0700 @@ -744,7 +744,15 @@ int pcibios_set_pcie_reset_state(struct static void __rtas_set_slot_reset(struct pci_dn *pdn) { - rtas_pci_slot_reset (pdn, 1); + struct pci_dev *dev = pdn->pcidev; + + /* Determine type of EEH reset required by device, + * default hot reset or fundamental reset + */ + if (dev->needs_freset) + rtas_pci_slot_reset(pdn, 3); + else + rtas_pci_slot_reset(pdn, 1); /* The PCI bus requires that the reset be held high for at least * a 100 milliseconds. We wait a bit longer 'just in case'. */