From patchwork Thu Aug 6 02:35:10 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hidetoshi Seto X-Patchwork-Id: 39505 Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id n762YGjo027272 for ; Thu, 6 Aug 2009 02:35:33 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751162AbZHFCfb (ORCPT ); Wed, 5 Aug 2009 22:35:31 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1751833AbZHFCfb (ORCPT ); Wed, 5 Aug 2009 22:35:31 -0400 Received: from fgwmail5.fujitsu.co.jp ([192.51.44.35]:60123 "EHLO fgwmail5.fujitsu.co.jp" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751162AbZHFCfa (ORCPT ); Wed, 5 Aug 2009 22:35:30 -0400 Received: from m4.gw.fujitsu.co.jp ([10.0.50.74]) by fgwmail5.fujitsu.co.jp (Fujitsu Gateway) with ESMTP id n762ZU9k022357 for (envelope-from seto.hidetoshi@jp.fujitsu.com); Thu, 6 Aug 2009 11:35:30 +0900 Received: from smail (m4 [127.0.0.1]) by outgoing.m4.gw.fujitsu.co.jp (Postfix) with ESMTP id 39D4545DE6F for ; Thu, 6 Aug 2009 11:35:30 +0900 (JST) Received: from s4.gw.fujitsu.co.jp (s4.gw.fujitsu.co.jp [10.0.50.94]) by m4.gw.fujitsu.co.jp (Postfix) with ESMTP id 1480C45DE79 for ; Thu, 6 Aug 2009 11:35:30 +0900 (JST) Received: from s4.gw.fujitsu.co.jp (localhost.localdomain [127.0.0.1]) by s4.gw.fujitsu.co.jp (Postfix) with ESMTP id B54E31DB8043 for ; Thu, 6 Aug 2009 11:35:29 +0900 (JST) Received: from ml14.s.css.fujitsu.com (ml14.s.css.fujitsu.com [10.249.87.104]) by s4.gw.fujitsu.co.jp (Postfix) with ESMTP id 63E691DB803A for ; Thu, 6 Aug 2009 11:35:26 +0900 (JST) Received: from ml14.css.fujitsu.com (ml14 [127.0.0.1]) by ml14.s.css.fujitsu.com (Postfix) with ESMTP id 3DC399F625E; Thu, 6 Aug 2009 11:35:26 +0900 (JST) Received: from [127.0.0.1] (unknown [10.124.100.141]) by ml14.s.css.fujitsu.com (Postfix) with ESMTP id 77CE69F6260; Thu, 6 Aug 2009 11:35:25 +0900 (JST) X-SecurityPolicyCheck-FJ: OK by FujitsuOutboundMailChecker v1.3.1 Received: from FMVDA2A041[10.124.100.141] by FMVDA2A041 (FujitsuOutboundMailChecker v1.3.1/9992[10.124.100.141]); Thu, 06 Aug 2009 11:35:17 +0900 (JST) Message-ID: <4A7A415E.2090303@jp.fujitsu.com> Date: Thu, 06 Aug 2009 11:35:10 +0900 From: Hidetoshi Seto User-Agent: Thunderbird 2.0.0.22 (Windows/20090605) MIME-Version: 1.0 To: linux-pci@vger.kernel.org CC: Jesse Barnes , Matthew Wilcox Subject: [PATCH 6/8] pci/msi: MSI-X cleanup, msix_program_entries() References: <4A7A4036.9020007@jp.fujitsu.com> In-Reply-To: <4A7A4036.9020007@jp.fujitsu.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Cleanup based on the prototype from Matthew Milcox. Signed-off-by: Hidetoshi Seto Reviewed-by: Matthew Wilcox --- drivers/pci/msi.c | 29 +++++++++++++++++++---------- 1 files changed, 19 insertions(+), 10 deletions(-) diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c index b0cc821..ce08d0b 100644 --- a/drivers/pci/msi.c +++ b/drivers/pci/msi.c @@ -447,6 +447,24 @@ static void __iomem *msix_map_region(struct pci_dev *dev, unsigned pos, return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); } +static void msix_program_entries(struct pci_dev *dev, + struct msix_entry *entries) +{ + struct msi_desc *entry; + int i = 0; + + list_for_each_entry(entry, &dev->msi_list, list) { + int offset = entries[i].entry * PCI_MSIX_ENTRY_SIZE + + PCI_MSIX_ENTRY_VECTOR_CTRL; + + entries[i].vector = entry->irq; + set_irq_msi(entry->irq, entry); + entry->masked = readl(entry->mask_base + offset); + msix_mask_irq(entry, 1); + i++; + } +} + /** * msix_capability_init - configure device's MSI-X capability * @dev: pointer to the pci_dev data structure of MSI-X device function @@ -511,16 +529,7 @@ static int msix_capability_init(struct pci_dev *dev, control |= PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE; pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); - i = 0; - list_for_each_entry(entry, &dev->msi_list, list) { - entries[i].vector = entry->irq; - set_irq_msi(entry->irq, entry); - j = entries[i].entry; - entry->masked = readl(base + j * PCI_MSIX_ENTRY_SIZE + - PCI_MSIX_ENTRY_VECTOR_CTRL); - msix_mask_irq(entry, 1); - i++; - } + msix_program_entries(dev, entries); /* Set MSI-X enabled bits and unmask the function */ pci_intx_for_msi(dev, 0);