From patchwork Tue Sep 15 08:34:05 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kenji Kaneshige X-Patchwork-Id: 47618 Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id n8F8YYPO016947 for ; Tue, 15 Sep 2009 08:34:34 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750945AbZIOIeU (ORCPT ); Tue, 15 Sep 2009 04:34:20 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1751043AbZIOIeU (ORCPT ); Tue, 15 Sep 2009 04:34:20 -0400 Received: from fgwmail6.fujitsu.co.jp ([192.51.44.36]:35482 "EHLO fgwmail6.fujitsu.co.jp" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750993AbZIOIeT (ORCPT ); Tue, 15 Sep 2009 04:34:19 -0400 Received: from m5.gw.fujitsu.co.jp ([10.0.50.75]) by fgwmail6.fujitsu.co.jp (Fujitsu Gateway) with ESMTP id n8F8YL1e025735 for (envelope-from kaneshige.kenji@jp.fujitsu.com); Tue, 15 Sep 2009 17:34:21 +0900 Received: from smail (m5 [127.0.0.1]) by outgoing.m5.gw.fujitsu.co.jp (Postfix) with ESMTP id ADDC245DE51 for ; Tue, 15 Sep 2009 17:34:21 +0900 (JST) Received: from s5.gw.fujitsu.co.jp (s5.gw.fujitsu.co.jp [10.0.50.95]) by m5.gw.fujitsu.co.jp (Postfix) with ESMTP id 8C51645DE4F for ; Tue, 15 Sep 2009 17:34:21 +0900 (JST) Received: from s5.gw.fujitsu.co.jp (localhost.localdomain [127.0.0.1]) by s5.gw.fujitsu.co.jp (Postfix) with ESMTP id 723A2E1800A for ; Tue, 15 Sep 2009 17:34:21 +0900 (JST) Received: from m108.s.css.fujitsu.com (m108.s.css.fujitsu.com [10.249.87.108]) by s5.gw.fujitsu.co.jp (Postfix) with ESMTP id 2EEA21DB803F for ; Tue, 15 Sep 2009 17:34:18 +0900 (JST) Received: from m108.css.fujitsu.com (m108 [127.0.0.1]) by m108.s.css.fujitsu.com (Postfix) with ESMTP id C0863B68003; Tue, 15 Sep 2009 17:34:17 +0900 (JST) Received: from [127.0.0.1] (unknown [10.124.100.137]) by m108.s.css.fujitsu.com (Postfix) with ESMTP id 487C0B68006; Tue, 15 Sep 2009 17:34:17 +0900 (JST) X-SecurityPolicyCheck-FJ: OK by FujitsuOutboundMailChecker v1.3.1 Received: from KANE-LIFEBOOK[10.124.100.137] by KANE-LIFEBOOK (FujitsuOutboundMailChecker v1.3.1/9992[10.124.100.137]); Tue, 15 Sep 2009 17:34:09 +0900 (JST) Message-ID: <4AAF517D.3010200@jp.fujitsu.com> Date: Tue, 15 Sep 2009 17:34:05 +0900 From: Kenji Kaneshige User-Agent: Thunderbird 2.0.0.23 (Windows/20090812) MIME-Version: 1.0 To: linux-pci@vger.kernel.org, jbarnes@virtuousgeek.org CC: ebiederm@xmission.com Subject: [PATCH 15/15] pciehp: remove slot capabilities definitions References: <4AAF4F16.802@jp.fujitsu.com> In-Reply-To: <4AAF4F16.802@jp.fujitsu.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Use generic PCIe slot capabilities register definitions instead of internal definitions. Signed-off-by: Kenji Kaneshige --- drivers/pci/hotplug/pciehp.h | 26 ++++++++------------------ 1 file changed, 8 insertions(+), 18 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Index: 20090915/drivers/pci/hotplug/pciehp.h =================================================================== --- 20090915.orig/drivers/pci/hotplug/pciehp.h +++ 20090915/drivers/pci/hotplug/pciehp.h @@ -117,24 +117,14 @@ struct controller { #define POWERON_STATE 3 #define POWEROFF_STATE 4 -/* Field definitions in Slot Capabilities Register */ -#define ATTN_BUTTN_PRSN 0x00000001 -#define PWR_CTRL_PRSN 0x00000002 -#define MRL_SENS_PRSN 0x00000004 -#define ATTN_LED_PRSN 0x00000008 -#define PWR_LED_PRSN 0x00000010 -#define HP_SUPR_RM_SUP 0x00000020 -#define EMI_PRSN 0x00020000 -#define NO_CMD_CMPL_SUP 0x00040000 - -#define ATTN_BUTTN(ctrl) ((ctrl)->slot_cap & ATTN_BUTTN_PRSN) -#define POWER_CTRL(ctrl) ((ctrl)->slot_cap & PWR_CTRL_PRSN) -#define MRL_SENS(ctrl) ((ctrl)->slot_cap & MRL_SENS_PRSN) -#define ATTN_LED(ctrl) ((ctrl)->slot_cap & ATTN_LED_PRSN) -#define PWR_LED(ctrl) ((ctrl)->slot_cap & PWR_LED_PRSN) -#define HP_SUPR_RM(ctrl) ((ctrl)->slot_cap & HP_SUPR_RM_SUP) -#define EMI(ctrl) ((ctrl)->slot_cap & EMI_PRSN) -#define NO_CMD_CMPL(ctrl) ((ctrl)->slot_cap & NO_CMD_CMPL_SUP) +#define ATTN_BUTTN(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_ABP) +#define POWER_CTRL(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_PCP) +#define MRL_SENS(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_MRLSP) +#define ATTN_LED(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_AIP) +#define PWR_LED(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_PIP) +#define HP_SUPR_RM(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_HPS) +#define EMI(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_EIP) +#define NO_CMD_CMPL(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_NCCS) #define PSN(ctrl) ((ctrl)->slot_cap >> 19) extern int pciehp_sysfs_enable_slot(struct slot *slot);