From patchwork Tue Dec 1 02:50:45 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yinghai Lu X-Patchwork-Id: 63836 Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id nB12pxDl005486 for ; Tue, 1 Dec 2009 02:51:59 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752302AbZLACvg (ORCPT ); Mon, 30 Nov 2009 21:51:36 -0500 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1752290AbZLACvg (ORCPT ); Mon, 30 Nov 2009 21:51:36 -0500 Received: from hera.kernel.org ([140.211.167.34]:41087 "EHLO hera.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752150AbZLACvf (ORCPT ); Mon, 30 Nov 2009 21:51:35 -0500 Received: from [10.6.76.26] (sca-ea-fw-1.Sun.COM [192.18.43.225]) (authenticated bits=0) by hera.kernel.org (8.14.3/8.14.3) with ESMTP id nB12paqc026566 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 1 Dec 2009 02:51:40 GMT Message-ID: <4B148485.3000107@kernel.org> Date: Mon, 30 Nov 2009 18:50:45 -0800 From: Yinghai Lu User-Agent: Thunderbird 2.0.0.23 (X11/20090817) MIME-Version: 1.0 To: Alex Williamson CC: jbarnes@virtuousgeek.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] PCI: Always set prefetchable base/limit upper32 registers References: <20091130212228.7555.43533.stgit@debian.lart> <4B143AE5.7040702@kernel.org> <1259617381.8949.281.camel@8530w.home> <4B143E83.6020105@kernel.org> <1259618496.8949.290.camel@8530w.home> <4B144346.50608@kernel.org> <1259619578.8949.295.camel@8530w.home> <4B1455FD.90002@kernel.org> <1259625224.8949.319.camel@8530w.home> <4B145C9D.70601@kernel.org> <1259632564.10482.10.camel@2710p.home> <4B147EE0.8080209@kernel.org> In-Reply-To: <4B147EE0.8080209@kernel.org> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Index: linux-2.6/drivers/pci/setup-bus.c =================================================================== --- linux-2.6.orig/drivers/pci/setup-bus.c +++ linux-2.6/drivers/pci/setup-bus.c @@ -289,7 +289,6 @@ static void pci_setup_bridge_mmio_pref(s struct resource *res; struct pci_bus_region region; u32 l, bu, lu; - int pref_mem64; /* Clear out the upper 32 bits of PREF limit. If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily @@ -297,7 +296,6 @@ static void pci_setup_bridge_mmio_pref(s pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0); /* Set up PREF base/limit. */ - pref_mem64 = 0; bu = lu = 0; res = bus->resource[2]; pcibios_resource_to_bus(bridge, ®ion, res); @@ -305,7 +303,6 @@ static void pci_setup_bridge_mmio_pref(s l = (region.start >> 16) & 0xfff0; l |= region.end & 0xfff00000; if (res->flags & IORESOURCE_MEM_64) { - pref_mem64 = 1; bu = upper_32_bits(region.start); lu = upper_32_bits(region.end); } @@ -317,7 +314,7 @@ static void pci_setup_bridge_mmio_pref(s } pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l); - if (pref_mem64) { + if (res->flags & PCI_PREF_RANGE_TYPE_64) { /* Set the upper 32 bits of PREF base & limit. */ pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu); pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu); @@ -385,8 +382,10 @@ static void pci_bridge_check_ranges(stru } if (pmem) { b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; - if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) + if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { b_res[2].flags |= IORESOURCE_MEM_64; + b_res[2].flags |= PCI_PREF_RANGE_TYPE_64; + } } /* double check if bridge does support 64 bit pref */ @@ -397,8 +396,10 @@ static void pci_bridge_check_ranges(stru pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, 0xffffffff); pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp); - if (!tmp) + if (!tmp) { b_res[2].flags &= ~IORESOURCE_MEM_64; + dev_info(&bridge->dev, "%pR MEM_64 cleared\n", &b_res[2]); + } pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, mem_base_hi); }