===================================================================
@@ -41,6 +41,9 @@ static inline void print_ioh_resources(s
#define IOH_LMMIOH_LIMITU 0x118
#define IOH_LCFGBUS 0x11c
+#define IOH_VTBAR 0x180
+#define IOH_VTSIZE 0x2000 /* Fixed HW size (not programmable) */
+
static void __devinit pci_root_bus_res(struct pci_dev *dev)
{
u16 word;
@@ -52,7 +55,7 @@ static void __devinit pci_root_bus_res(s
int bus_base, bus_end;
/* some sys doesn't get mmconf enabled */
- if (dev->cfg_size < 0x120)
+ if (dev->cfg_size < 0x200)
return;
if (pci_root_num >= PCI_ROOT_NR) {
@@ -78,7 +81,45 @@ static void __devinit pci_root_bus_res(s
pci_read_config_dword(dev, IOH_LMMIOL, &dword);
mmiol_base = (dword & 0xff00) << (24 - 8);
mmiol_end = (dword & 0xff000000) | 0xffffff;
- update_res(info, mmiol_base, mmiol_end, IORESOURCE_MEM, 0);
+ pci_read_config_dword(dev, IOH_VTBAR, &dword);
+ if (dword & 0x1) {
+ u32 vt_base, vt_end;
+ u32 overlap_base, overlap_end;
+
+ vt_base = dword & 0xfffffffe;
+ vt_end = vt_base + IOH_VTSIZE - 1;
+
+ /* totally covered by vt range? */
+ if (mmiol_base >= vt_base && mmiol_end <= vt_end)
+ goto out;
+
+ /* vt range is totally covered? */
+ if (mmiol_base < vt_base && mmiol_end > vt_end) {
+ update_res(info, mmiol_base, vt_base - 1,
+ IORESOURCE_MEM, 0);
+ update_res(info, vt_end + 1, mmiol_end,
+ IORESOURCE_MEM, 0);
+ goto out;
+ }
+
+ /* partially covered */
+ overlap_base = max(vt_base, mmiol_base);
+ overlap_end = min(vt_end, mmiol_end);
+ if (overlap_base > overlap_end)
+ update_res(info, mmiol_base, mmiol_end,
+ IORESOURCE_MEM, 0);
+
+ /* left range could be head or tail */
+ if (mmiol_base < overlap_base)
+ update_res(info, mmiol_base, overlap_base - 1,
+ IORESOURCE_MEM, 0);
+ else
+ update_res(info, overlap_end + 1, mmiol_end,
+ IORESOURCE_MEM, 0);
+out:
+ ;
+ } else
+ update_res(info, mmiol_base, mmiol_end, IORESOURCE_MEM, 0);
pci_read_config_dword(dev, IOH_LMMIOH, &dword);
mmioh_base = ((u64)(dword & 0xfc00)) << (26 - 10);