From patchwork Wed Oct 13 06:00:23 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hidetoshi Seto X-Patchwork-Id: 249741 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id o9D61BYE025244 for ; Wed, 13 Oct 2010 06:01:11 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752600Ab0JMGBL (ORCPT ); Wed, 13 Oct 2010 02:01:11 -0400 Received: from fgwmail7.fujitsu.co.jp ([192.51.44.37]:50853 "EHLO fgwmail7.fujitsu.co.jp" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752528Ab0JMGBK (ORCPT ); Wed, 13 Oct 2010 02:01:10 -0400 Received: from m4.gw.fujitsu.co.jp ([10.0.50.74]) by fgwmail7.fujitsu.co.jp (Fujitsu Gateway) with ESMTP id o9D618N2028733 for (envelope-from seto.hidetoshi@jp.fujitsu.com); Wed, 13 Oct 2010 15:01:09 +0900 Received: from smail (m4 [127.0.0.1]) by outgoing.m4.gw.fujitsu.co.jp (Postfix) with ESMTP id 4596845DE7F for ; Wed, 13 Oct 2010 15:01:08 +0900 (JST) Received: from s4.gw.fujitsu.co.jp (s4.gw.fujitsu.co.jp [10.0.50.94]) by m4.gw.fujitsu.co.jp (Postfix) with ESMTP id F3ED445DE7B for ; Wed, 13 Oct 2010 15:01:07 +0900 (JST) Received: from s4.gw.fujitsu.co.jp (localhost.localdomain [127.0.0.1]) by s4.gw.fujitsu.co.jp (Postfix) with ESMTP id DF276EF8002 for ; Wed, 13 Oct 2010 15:01:07 +0900 (JST) Received: from m105.s.css.fujitsu.com (m105.s.css.fujitsu.com [10.249.87.105]) by s4.gw.fujitsu.co.jp (Postfix) with ESMTP id 9CA8E1DB803A for ; Wed, 13 Oct 2010 15:01:07 +0900 (JST) Received: from m105.css.fujitsu.com (m105 [127.0.0.1]) by m105.s.css.fujitsu.com (Postfix) with ESMTP id 6E8425E8002; Wed, 13 Oct 2010 15:01:07 +0900 (JST) Received: from [127.0.0.1] (unknown [10.124.101.144]) by m105.s.css.fujitsu.com (Postfix) with ESMTP id 10BEE5D8002; Wed, 13 Oct 2010 15:01:07 +0900 (JST) X-SecurityPolicyCheck-FJ: OK by FujitsuOutboundMailChecker v1.3.1 Received: from FMVDA2A041[10.124.101.144] by FMVDA2A041 (FujitsuOutboundMailChecker v1.3.1/9992[10.124.101.144]); Wed, 13 Oct 2010 15:01:01 +0900 (JST) Message-ID: <4CB54AF7.7070109@jp.fujitsu.com> Date: Wed, 13 Oct 2010 15:00:23 +0900 From: Hidetoshi Seto User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.0; ja; rv:1.9.2.9) Gecko/20100915 Thunderbird/3.1.4 MIME-Version: 1.0 To: linux-pci@vger.kernel.org CC: Jesse Barnes Subject: [PATCH] PCI: add PCI_MSIX_TABLE/PBA defines Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter1.kernel.org [140.211.167.41]); Wed, 13 Oct 2010 06:01:12 +0000 (UTC) diff --git a/drivers/pci/msi.h b/drivers/pci/msi.h index de27c1c..feff3be 100644 --- a/drivers/pci/msi.h +++ b/drivers/pci/msi.h @@ -22,8 +22,8 @@ #define is_64bit_address(control) (!!(control & PCI_MSI_FLAGS_64BIT)) #define is_mask_bit_support(control) (!!(control & PCI_MSI_FLAGS_MASKBIT)) -#define msix_table_offset_reg(base) (base + 0x04) -#define msix_pba_offset_reg(base) (base + 0x08) +#define msix_table_offset_reg(base) (base + PCI_MSIX_TABLE) +#define msix_pba_offset_reg(base) (base + PCI_MSIX_PBA) #define msix_table_size(control) ((control & PCI_MSIX_FLAGS_QSIZE)+1) #define multi_msix_capable(control) msix_table_size((control)) diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h index 455b9cc..af83076 100644 --- a/include/linux/pci_regs.h +++ b/include/linux/pci_regs.h @@ -300,12 +300,14 @@ #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */ #define PCI_MSI_MASK_64 16 /* Mask bits register for 64-bit devices */ -/* MSI-X registers (these are at offset PCI_MSIX_FLAGS) */ +/* MSI-X registers */ #define PCI_MSIX_FLAGS 2 #define PCI_MSIX_FLAGS_QSIZE 0x7FF #define PCI_MSIX_FLAGS_ENABLE (1 << 15) #define PCI_MSIX_FLAGS_MASKALL (1 << 14) -#define PCI_MSIX_FLAGS_BIRMASK (7 << 0) +#define PCI_MSIX_TABLE 4 +#define PCI_MSIX_PBA 8 +#define PCI_MSIX_FLAGS_BIRMASK (7 << 0) /* CompactPCI Hotswap Register */