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Fri, 20 Jul 2018 12:48:00 +0000 From: Leonard Crestez To: Lucas Stach , Richard Zhu , Andrey Smirnov Cc: Shawn Guo , Joao Pinto , Jingoo Han , Bjorn Helgaas , Lorenzo Pieralisi , linux-pci@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Fabio Estevam , Dong Aisheng , kernel@pengutronix.de, linux-imx@nxp.com Subject: [PATCH v2 2/3] reset: imx7: Fix always writing bits as 0 Date: Fri, 20 Jul 2018 15:47:43 +0300 Message-Id: <54f436a1d2a11a379af642a3327312367ef95343.1532090446.git.leonard.crestez@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [95.76.156.53] X-ClientProxiedBy: AM5PR06CA0015.eurprd06.prod.outlook.com (2603:10a6:206:2::28) To AM6PR04MB4293.eurprd04.prod.outlook.com (2603:10a6:209:4f::31) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 0fcfbf11-5e4d-474c-45f4-08d5ee3f0705 X-MS-Office365-Filtering-HT: Tenant X-Microsoft-Antispam: UriScan:; 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Fix this by writing 1 or 0 respectively. The reference manual is not very clear regarding SRC_PCIEPHY_RCR but for other registers like MIPIPHY and HSICPHY the bits are explicitly documented as "1 means assert, 0 means deassert". The values are still reversed for IMX7_RESET_PCIE_CTRL_APPS_EN. Signed-off-by: Leonard Crestez Reviewed-by: Lucas Stach --- drivers/reset/reset-imx7.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/reset/reset-imx7.c b/drivers/reset/reset-imx7.c index 4db177bc89bc..fdeac1946429 100644 --- a/drivers/reset/reset-imx7.c +++ b/drivers/reset/reset-imx7.c @@ -78,11 +78,11 @@ static struct imx7_src *to_imx7_src(struct reset_controller_dev *rcdev) static int imx7_reset_set(struct reset_controller_dev *rcdev, unsigned long id, bool assert) { struct imx7_src *imx7src = to_imx7_src(rcdev); const struct imx7_src_signal *signal = &imx7_src_signals[id]; - unsigned int value = 0; + unsigned int value = assert ? signal->bit : 0; switch (id) { case IMX7_RESET_PCIEPHY: /* * wait for more than 10us to release phy g_rst and