From patchwork Mon Apr 27 20:27:06 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Murali Karicheri X-Patchwork-Id: 6282421 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 650269F326 for ; Mon, 27 Apr 2015 20:27:32 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id EB2B220374 for ; Mon, 27 Apr 2015 20:27:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 000412035B for ; Mon, 27 Apr 2015 20:27:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965042AbbD0U11 (ORCPT ); Mon, 27 Apr 2015 16:27:27 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:50910 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S964964AbbD0U11 (ORCPT ); Mon, 27 Apr 2015 16:27:27 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id t3RKR2a2032116; Mon, 27 Apr 2015 15:27:02 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id t3RKR1it007336; Mon, 27 Apr 2015 15:27:01 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.224.2; Mon, 27 Apr 2015 15:27:00 -0500 Received: from [158.218.104.195] (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id t3RKQxlu005488; Mon, 27 Apr 2015 15:27:00 -0500 Message-ID: <553E9B9A.5090000@ti.com> Date: Mon, 27 Apr 2015 16:27:06 -0400 From: Murali Karicheri User-Agent: Mozilla/5.0 (X11; Linux i686; rv:12.0) Gecko/20120430 Thunderbird/12.0.1 MIME-Version: 1.0 To: Jingoo Han , Mohit Kumar , Lucas Stach , KISHON VIJAY , "linux-pci@vger.kernel.org" , "devicetree@vger.kernel.org" , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Bjorn Helgaas Subject: [RFC] PCI: designware: missing *config* reg space Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP All, I would like to take action to resolve the following print message thrown by PCI designware core driver when kernel boots up on Keystone. [ 0.415778] keystone-pcie 21801000.pcie: missing *config* reg space As per DT documentation introduced by commit 4dd964df36d0e548e1806ec2ec275b62d4dc46e8 "PCI: designware: Look for configuration space in 'reg', not 'ranges' This is introduced to stop abusing the range property for defining resource for config space. However if the device binding doesn't have reg-name = "config" defined, this throws out an unnecessary log message at boot which seems to me not right. AFAIK, reg-names is not mandatory. config space address in Keystone case is defined using index. So for keystone this needs to be fixed. I propose to add the following check in the designware code to address this. Keystone uses an older version of the Designware IP and doesn't have the ATU support. So va_cfg0_base and va_cfg1_base are already set up in ks_dw_pcie_host_init() before calling dw_pcie_host_init() and points to the remote config space address (both same for keystone). I think for other DW drivers, these variables are NULL. So add a check and avoid this error message for Keystone. Any comments? pp->cfg1_size = resource_size(cfg_res)/2; @@ -372,7 +376,8 @@ int dw_pcie_host_init(struct pcie_port *pp) pp->cfg0_mod_base = of_read_number(addrp, ns); pp->cfg1_mod_base = pp->cfg0_mod_base + pp->cfg0_size; } else { - dev_err(pp->dev, "missing *config* reg space\n"); + if (!pp->va_cfg0_base && !pp->va_cfg1_base) + dev_err(pp->dev, "missing *config* reg space\n"); } --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -348,7 +348,7 @@ int dw_pcie_host_init(struct pcie_port *pp) struct platform_device *pdev = to_platform_device(pp->dev); struct of_pci_range range; struct of_pci_range_parser parser; - struct resource *cfg_res; + struct resource *cfg_res = NULL; u32 val, na, ns; const __be32 *addrp; int i, index, ret; @@ -359,7 +359,11 @@ int dw_pcie_host_init(struct pcie_port *pp) of_property_read_u32(np, "#address-cells", &na); ns = of_n_size_cells(np); - cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); + if (!pp->va_cfg0_base && !pp->va_cfg0_base) + cfg_res = platform_get_resource_byname(pdev, + IORESOURCE_MEM, + "config"); + if (cfg_res) { pp->cfg0_size = resource_size(cfg_res)/2;