From patchwork Sat Sep 3 02:37:24 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Lin X-Patchwork-Id: 9311853 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id BB0CC60760 for ; Sat, 3 Sep 2016 02:50:27 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AB571297B1 for ; Sat, 3 Sep 2016 02:50:27 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9752C297B0; Sat, 3 Sep 2016 02:50:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_TVD_MIME_EPI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9464A296F4 for ; Sat, 3 Sep 2016 02:50:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752723AbcICCuV (ORCPT ); Fri, 2 Sep 2016 22:50:21 -0400 Received: from lucky1.263xmail.com ([211.157.147.136]:49624 "EHLO lucky1.263xmail.com" rhost-flags-OK-FAIL-OK-OK) by vger.kernel.org with ESMTP id S1752695AbcICCuU (ORCPT ); Fri, 2 Sep 2016 22:50:20 -0400 X-Greylist: delayed 754 seconds by postgrey-1.27 at vger.kernel.org; Fri, 02 Sep 2016 22:50:18 EDT Received: from shawn.lin?rock-chips.com (unknown [192.168.167.156]) by lucky1.263xmail.com (Postfix) with ESMTP id E947DCA; Sat, 3 Sep 2016 10:37:38 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED: 0 Received: from [172.16.12.182] (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTP id 7C31A406; Sat, 3 Sep 2016 10:37:37 +0800 (CST) X-RL-SENDER: shawn.lin@rock-chips.com X-FST-TO: linux@roeck-us.net X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: shawn.lin@rock-chips.com X-UNIQUE-TAG: <3a603658da21b573afa1b9f64eacc0f6> X-ATTACHMENT-NUM: 1 X-SENDER: lintao@rock-chips.com X-DNS-TYPE: 0 Received: from [172.16.12.182] (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith ESMTP id 25537URSSTF; Sat, 03 Sep 2016 10:37:39 +0800 (CST) Subject: Re: [PATCH v2 00/15] PCI: rockchip: Cleanups against v10 To: Bjorn Helgaas References: <20160902154501.8650.99790.stgit@bhelgaas-glaptop2.roam.corp.google.com> Cc: shawn.lin@rock-chips.com, devicetree@vger.kernel.org, Wenrui Li , Heiko Stuebner , Arnd Bergmann , Marc Zyngier , linux-pci@vger.kernel.org, Brian Norris , linux-kernel@vger.kernel.org, Doug Anderson , linux-rockchip@lists.infradead.org, Rob Herring , Guenter Roeck From: Shawn Lin Message-ID: <5d1e6d5f-c8d9-8fcd-41dd-cabc3027f66a@rock-chips.com> Date: Sat, 3 Sep 2016 10:37:24 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.3; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.3.0 MIME-Version: 1.0 In-Reply-To: <20160902154501.8650.99790.stgit@bhelgaas-glaptop2.roam.corp.google.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Hi Bjorn, On 2016/9/2 23:53, Bjorn Helgaas wrote: > These are cleanups against 2098142ae87d, the current pci/host-rockchip > head in my tree. > Thanks so much for you to help clean up this driver, since I think it should be my duty to take over this. Hope not too late for me to help your cleanup. I think the v2 cannot compile gracefully without the appended patch. After fixing these compile errors, I backported this driver entirely to my downstream 4.4 tree and it worked fine without regression. Once again, thanks for doing this. :) > Changes from v1: > > - Rework HIWORD_UPDATE > - Remove duplicate CSR definitions > - Move CSR block offset from read/write caller to CSR definition > - Organize CSRs into logical blocks > - Fix some inconsistent CSR names > - Add names for registers at the base of CSR blocks > > I was disappointed to find how disorganized the v10 CSR definitions were. > It was quite a hodgepodge. I should have noticed that earlier, but as > penance, I tried to clean it up myself. > > These are in git as pci/host-rockchip-wip. Again, I intend to squash these > all into the single commit that adds the driver when I finally merge it. > > --- > > Bjorn Helgaas (15): > Remove unused symbols, unnecessary parens, other minor comments from > Rename pcie_read() and pcie_write() to rockchip_pcie_read() and > Always use "rockchip" as the pointer to per-device struct. > Rename struct rockchip_pcie_port to struct rockchip_pcie. > Use a local "dev" to avoid repetition of "rockchip->dev". > Add comment about why 32-bit read/modify/write isn't safe. > Simplify the confusing HIWORD_UPDATE scheme. > Remove duplicate CSR definition. > Move CSR bases into definition. > Group related CSR definitions together. > Rename PCIE_CORE_RC_CONF_SCC_SHIFT to match similar definitions. > Rename ROCKCHIP_PCIE_RPIFR1_INTR_MASK and ROCKCHIP_PCIE_RPIFR1_INTR_SHIFT > The register at PCIE_CLIENT_BASE presumably has a name of its own. Add a > Simplify testing of link status and speed testing. > Move msleeps to address Guenter's comments. > > > drivers/pci/host/pcie-rockchip.c | 842 ++++++++++++++++++-------------------- > 1 file changed, 391 insertions(+), 451 deletions(-) > > > diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c index 754d24b..2bc1c35 100644 --- a/drivers/pci/host/pcie-rockchip.c +++ b/drivers/pci/host/pcie-rockchip.c @@ -931,7 +931,7 @@ static int rockchip_pcie_prog_ob_atu(struct rockchip_pcie *rockchip, u32 ob_addr_0; u32 ob_addr_1; u32 ob_desc_0; - void __iomem *aw_offset; + u32 aw_offset; if (region_no >= MAX_AXI_WRAPPER_REGION_NUM) return -EINVAL; @@ -955,13 +955,13 @@ static int rockchip_pcie_prog_ob_atu(struct rockchip_pcie *rockchip, ob_addr_1 = upper_addr; ob_desc_0 = (1 << 23 | type); - rockchip_pcie_writel(rockchip, ob_addr_0, + rockchip_pcie_write(rockchip, ob_addr_0, PCIE_CORE_OB_REGION_ADDR0 + aw_offset); - rockchip_pcie_writel(rockchip, ob_addr_1, + rockchip_pcie_write(rockchip, ob_addr_1, PCIE_CORE_OB_REGION_ADDR1 + aw_offset); - rockchip_pcie_writel(rockchip, ob_desc_0, + rockchip_pcie_write(rockchip, ob_desc_0, PCIE_CORE_OB_REGION_DESC0 + aw_offset); - rockchip_pcie_writel(rockchip, 0, + rockchip_pcie_write(rockchip, 0, PCIE_CORE_OB_REGION_DESC1 + aw_offset); return 0; @@ -973,7 +973,7 @@ static int rockchip_pcie_prog_ib_atu(struct rockchip_pcie *rockchip, { u32 ib_addr_0; u32 ib_addr_1; - void __iomem *aw_offset; + u32 aw_offset; if (region_no > MAX_AXI_IB_ROOTPORT_REGION_NUM) return -EINVAL; @@ -988,8 +988,8 @@ static int rockchip_pcie_prog_ib_atu(struct rockchip_pcie *rockchip, ib_addr_0 |= (lower_addr << 8) & PCIE_CORE_IB_REGION_ADDR0_LO_ADDR; ib_addr_1 = upper_addr; - rockchip_pcie_writel(rockchip, ib_addr_0, PCIE_RP_IB_ADDR0 + aw_offset); - rockchip_pcie_writel(rockchip, ib_addr_1, PCIE_RP_IB_ADDR1 + aw_offset); + rockchip_pcie_write(rockchip, ib_addr_0, PCIE_RP_IB_ADDR0 + aw_offset); + rockchip_pcie_write(rockchip, ib_addr_1, PCIE_RP_IB_ADDR1 + aw_offset); return 0; }