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[2003:ea:8bd4:d600:e9e9:fd8e:c5c4:d5d8]) by smtp.googlemail.com with ESMTPSA id y14-v6sm13353100wrq.45.2018.08.05.13.31.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 05 Aug 2018 13:31:10 -0700 (PDT) Subject: [PATCH v2] PCI: set flag IRQCHIP_ONESHOT_SAFE for PCI-MSI irqchip's From: Heiner Kallweit To: Bjorn Helgaas , Thomas Gleixner Cc: "linux-pci@vger.kernel.org" References: <9f18bc20-cf27-bc3c-71e5-4e24a6c983c7@gmail.com> Message-ID: <70984d26-1d35-d925-f67b-698ed85bbab5@gmail.com> Date: Sun, 5 Aug 2018 22:31:03 +0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 In-Reply-To: <9f18bc20-cf27-bc3c-71e5-4e24a6c983c7@gmail.com> Content-Language: en-US Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP If flag IRQCHIP_ONESHOT_SAFE isn't set for an irqchip and we have a threaded interrupt with no primary handler, then flag IRQF_ONESHOT needs to be set for the interrupt, causing some overhead in the threaded interrupt handler. For more detailed explanation also check following comment in __setup_irq(): The interrupt was requested with handler = NULL, so we use the default primary handler for it. But it does not have the oneshot flag set. In combination with level interrupts this is deadly, because the default primary handler just wakes the thread, then the irq lines is reenabled, but the device still has the level irq asserted. Rinse and repeat.... While this works for edge type interrupts, we play it safe and reject unconditionally because we can't say for sure which type this interrupt really has. The type flags are unreliable as the underlying chip implementation can override them. Another comment in __setup_irq() gives a hint already that this overhead can be avoided for PCI-MSI: Some irq chips like MSI based interrupts are per se one shot safe. Check the chip flags, so we can avoid the unmask dance at the end of the threaded handler for those. Following this let's mark all PCI-MSI irqchip's as oneshot-safe. See also discussion here: https://marc.info/?l=linux-pci&m=153332526101128&w=2 Signed-off-by: Heiner Kallweit --- v2: - extended commit message --- drivers/pci/msi.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c index 4d88afdf..f2ef8964 100644 --- a/drivers/pci/msi.c +++ b/drivers/pci/msi.c @@ -1446,6 +1446,9 @@ struct irq_domain *pci_msi_create_irq_domain(struct fwnode_handle *fwnode, if (IS_ENABLED(CONFIG_GENERIC_IRQ_RESERVATION_MODE)) info->flags |= MSI_FLAG_MUST_REACTIVATE; + /* PCI-MSI is oneshot-safe */ + info->chip->flags |= IRQCHIP_ONESHOT_SAFE; + domain = msi_create_irq_domain(fwnode, info, parent); if (!domain) return NULL;