From patchwork Fri Aug 2 00:06:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kuppuswamy Sathyanarayanan X-Patchwork-Id: 11071623 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9E79D14DB for ; Fri, 2 Aug 2019 00:09:12 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8DDEC287A8 for ; Fri, 2 Aug 2019 00:09:12 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8228B287AF; Fri, 2 Aug 2019 00:09:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DD46F287A8 for ; Fri, 2 Aug 2019 00:09:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729929AbfHBAJK (ORCPT ); Thu, 1 Aug 2019 20:09:10 -0400 Received: from mga02.intel.com ([134.134.136.20]:59857 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728268AbfHBAIr (ORCPT ); Thu, 1 Aug 2019 20:08:47 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Aug 2019 17:08:44 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,336,1559545200"; d="scan'208";a="177993965" Received: from skuppusw-desk.jf.intel.com ([10.54.74.33]) by orsmga006.jf.intel.com with ESMTP; 01 Aug 2019 17:08:44 -0700 From: sathyanarayanan.kuppuswamy@linux.intel.com To: bhelgaas@google.com Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, ashok.raj@intel.com, keith.busch@intel.com, sathyanarayanan.kuppuswamy@linux.intel.com Subject: [PATCH v5 4/7] PCI/ATS: Add PRI support for PCIe VF devices Date: Thu, 1 Aug 2019 17:06:01 -0700 Message-Id: <827d051ef8c8bbfa815908ce927e607870780cb6.1564702313.git.sathyanarayanan.kuppuswamy@linux.intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Kuppuswamy Sathyanarayanan When IOMMU tries to enable Page Request Interface (PRI) for VF device in iommu_enable_dev_iotlb(), it always fails because PRI support for PCIe VF device is currently broken. Current implementation expects the given PCIe device (PF & VF) to implement PRI capability before enabling the PRI support. But this assumption is incorrect. As per PCIe spec r4.0, sec 9.3.7.11, all VFs associated with PF can only use the PRI of the PF and not implement it. Hence we need to create exception for handling the PRI support for PCIe VF device. Also, since PRI is a shared resource between PF/VF, following rules should apply. 1. Use proper locking before accessing/modifying PF resources in VF PRI enable/disable call. 2. Use reference count logic to track the usage of PRI resource. 3. Disable PRI only if the PRI reference count (pri_ref_cnt) is zero. Cc: Ashok Raj Cc: Keith Busch Suggested-by: Ashok Raj Signed-off-by: Kuppuswamy Sathyanarayanan --- drivers/pci/ats.c | 143 ++++++++++++++++++++++++++++++++++---------- include/linux/pci.h | 2 + 2 files changed, 112 insertions(+), 33 deletions(-) diff --git a/drivers/pci/ats.c b/drivers/pci/ats.c index 1f4be27a071d..079dc5444444 100644 --- a/drivers/pci/ats.c +++ b/drivers/pci/ats.c @@ -189,6 +189,8 @@ void pci_pri_init(struct pci_dev *pdev) if (pdev->is_virtfn) return; + mutex_init(&pdev->pri_lock); + pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); if (!pos) return; @@ -221,29 +223,57 @@ int pci_enable_pri(struct pci_dev *pdev, u32 reqs) { u16 control, status; u32 max_requests; + int ret = 0; + struct pci_dev *pf = pci_physfn(pdev); - if (WARN_ON(pdev->pri_enabled)) - return -EBUSY; + mutex_lock(&pf->pri_lock); - if (!pdev->pri_cap) - return -EINVAL; + if (WARN_ON(pdev->pri_enabled)) { + ret = -EBUSY; + goto pri_unlock; + } - pci_read_config_word(pdev, pdev->pri_cap + PCI_PRI_STATUS, &status); - if (!(status & PCI_PRI_STATUS_STOPPED)) - return -EBUSY; + if (!pf->pri_cap) { + ret = -EINVAL; + goto pri_unlock; + } + + if (pdev->is_virtfn && pf->pri_enabled) + goto update_status; + + /* + * Before updating PRI registers, make sure there is no + * outstanding PRI requests. + */ + pci_read_config_word(pf, pf->pri_cap + PCI_PRI_STATUS, &status); + if (!(status & PCI_PRI_STATUS_STOPPED)) { + ret = -EBUSY; + goto pri_unlock; + } - pci_read_config_dword(pdev, pdev->pri_cap + PCI_PRI_MAX_REQ, - &max_requests); + pci_read_config_dword(pf, pf->pri_cap + PCI_PRI_MAX_REQ, &max_requests); reqs = min(max_requests, reqs); - pdev->pri_reqs_alloc = reqs; - pci_write_config_dword(pdev, pdev->pri_cap + PCI_PRI_ALLOC_REQ, reqs); + pf->pri_reqs_alloc = reqs; + pci_write_config_dword(pf, pf->pri_cap + PCI_PRI_ALLOC_REQ, reqs); control = PCI_PRI_CTRL_ENABLE; - pci_write_config_word(pdev, pdev->pri_cap + PCI_PRI_CTRL, control); + pci_write_config_word(pf, pf->pri_cap + PCI_PRI_CTRL, control); - pdev->pri_enabled = 1; + /* + * If PRI is not already enabled in PF, increment the PF + * pri_ref_cnt to track the usage of PRI interface. + */ + if (pdev->is_virtfn && !pf->pri_enabled) { + atomic_inc(&pf->pri_ref_cnt); + pf->pri_enabled = 1; + } - return 0; +update_status: + atomic_inc(&pf->pri_ref_cnt); + pdev->pri_enabled = 1; +pri_unlock: + mutex_unlock(&pf->pri_lock); + return ret; } EXPORT_SYMBOL_GPL(pci_enable_pri); @@ -256,18 +286,30 @@ EXPORT_SYMBOL_GPL(pci_enable_pri); void pci_disable_pri(struct pci_dev *pdev) { u16 control; + struct pci_dev *pf = pci_physfn(pdev); - if (WARN_ON(!pdev->pri_enabled)) - return; + mutex_lock(&pf->pri_lock); - if (!pdev->pri_cap) - return; + if (WARN_ON(!pdev->pri_enabled) || !pf->pri_cap) + goto pri_unlock; + + atomic_dec(&pf->pri_ref_cnt); - pci_read_config_word(pdev, pdev->pri_cap + PCI_PRI_CTRL, &control); + /* + * If pri_ref_cnt is not zero, then don't modify hardware + * registers. + */ + if (atomic_read(&pf->pri_ref_cnt)) + goto done; + + pci_read_config_word(pf, pf->pri_cap + PCI_PRI_CTRL, &control); control &= ~PCI_PRI_CTRL_ENABLE; - pci_write_config_word(pdev, pdev->pri_cap + PCI_PRI_CTRL, control); + pci_write_config_word(pf, pf->pri_cap + PCI_PRI_CTRL, control); +done: pdev->pri_enabled = 0; +pri_unlock: + mutex_unlock(&pf->pri_lock); } EXPORT_SYMBOL_GPL(pci_disable_pri); @@ -277,17 +319,31 @@ EXPORT_SYMBOL_GPL(pci_disable_pri); */ void pci_restore_pri_state(struct pci_dev *pdev) { - u16 control = PCI_PRI_CTRL_ENABLE; - u32 reqs = pdev->pri_reqs_alloc; + u16 control; + u32 reqs; + struct pci_dev *pf = pci_physfn(pdev); if (!pdev->pri_enabled) return; - if (!pdev->pri_cap) + if (!pf->pri_cap) return; - pci_write_config_dword(pdev, pdev->pri_cap + PCI_PRI_ALLOC_REQ, reqs); - pci_write_config_word(pdev, pdev->pri_cap + PCI_PRI_CTRL, control); + mutex_lock(&pf->pri_lock); + + /* If PRI is already enabled by other VF's or PF, return */ + pci_read_config_word(pf, pf->pri_cap + PCI_PRI_CTRL, &control); + if (control & PCI_PRI_CTRL_ENABLE) + goto pri_unlock; + + reqs = pf->pri_reqs_alloc; + control = PCI_PRI_CTRL_ENABLE; + + pci_write_config_dword(pf, pf->pri_cap + PCI_PRI_ALLOC_REQ, reqs); + pci_write_config_word(pf, pf->pri_cap + PCI_PRI_CTRL, control); + +pri_unlock: + mutex_unlock(&pf->pri_lock); } EXPORT_SYMBOL_GPL(pci_restore_pri_state); @@ -300,18 +356,32 @@ EXPORT_SYMBOL_GPL(pci_restore_pri_state); */ int pci_reset_pri(struct pci_dev *pdev) { + struct pci_dev *pf = pci_physfn(pdev); u16 control; + int ret = 0; - if (WARN_ON(pdev->pri_enabled)) - return -EBUSY; + mutex_lock(&pf->pri_lock); - if (!pdev->pri_cap) - return -EINVAL; + if (WARN_ON(pdev->pri_enabled)) { + ret = -EBUSY; + goto done; + } + + if (!pf->pri_cap) { + ret = -EINVAL; + goto done; + } + + /* If PRI is already enabled by other VF's or PF, return 0 */ + if (pf->pri_enabled) + goto done; control = PCI_PRI_CTRL_RESET; - pci_write_config_word(pdev, pdev->pri_cap + PCI_PRI_CTRL, control); - return 0; + pci_write_config_word(pf, pf->pri_cap + PCI_PRI_CTRL, control); +done: + mutex_unlock(&pf->pri_lock); + return ret; } EXPORT_SYMBOL_GPL(pci_reset_pri); #endif /* CONFIG_PCI_PRI */ @@ -475,11 +545,18 @@ EXPORT_SYMBOL_GPL(pci_pasid_features); int pci_prg_resp_pasid_required(struct pci_dev *pdev) { u16 status; + struct pci_dev *pf = pci_physfn(pdev); + + mutex_lock(&pf->pri_lock); - if (!pdev->pri_cap) + if (!pf->pri_cap) { + mutex_unlock(&pf->pri_lock); return 0; + } + + pci_read_config_word(pf, pf->pri_cap + PCI_PRI_STATUS, &status); - pci_read_config_word(pdev, pdev->pri_cap + PCI_PRI_STATUS, &status); + mutex_unlock(&pf->pri_lock); if (status & PCI_PRI_STATUS_PASID) return 1; diff --git a/include/linux/pci.h b/include/linux/pci.h index 27224c0db849..3c9c4c82be27 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -455,8 +455,10 @@ struct pci_dev { atomic_t ats_ref_cnt; /* Number of VFs with ATS enabled */ #endif #ifdef CONFIG_PCI_PRI + struct mutex pri_lock; /* PRI enable lock */ u16 pri_cap; /* PRI Capability offset */ u32 pri_reqs_alloc; /* Number of PRI requests allocated */ + atomic_t pri_ref_cnt; /* Number of PF/VF PRI users */ #endif #ifdef CONFIG_PCI_PASID u16 pasid_cap; /* PASID Capability offset */