From patchwork Wed Apr 16 02:29:36 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yinghai Lu X-Patchwork-Id: 3996751 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 26C339F2CC for ; Wed, 16 Apr 2014 02:29:41 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 35E5C20221 for ; Wed, 16 Apr 2014 02:29:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 47C9A201FE for ; Wed, 16 Apr 2014 02:29:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750969AbaDPC3i (ORCPT ); Tue, 15 Apr 2014 22:29:38 -0400 Received: from mail-ig0-f169.google.com ([209.85.213.169]:60711 "EHLO mail-ig0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750919AbaDPC3h (ORCPT ); Tue, 15 Apr 2014 22:29:37 -0400 Received: by mail-ig0-f169.google.com with SMTP id h18so542622igc.2 for ; Tue, 15 Apr 2014 19:29:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:sender:in-reply-to:references:date:message-id:subject :from:to:cc:content-type; bh=ytwzFeWZHaPn+pf/pcfOo4eAVwLFryWrLYbw4b/g+Dg=; b=hovh86+LS9PNEULlh7ZQIR555BB0Sisi54kK53krEcWbNIyFYGfVQ22HChoIqMnuHe ukFvLaaa5klQDbAWzgzqT+mDCBw6vaTEoeHo/ChCQv4+JJg1ygy4Z8XWiM2Z5v5SgAaq vu36wefnoCbJw0UqVrUQ7ELyyDLLiQ6d+xnIhNkt1taE835OH8MsD7e4i5t47moBtwt5 hDGrQi67DsQmZONX/FffiuofSV+Vwb2qF/i9XfC/t6SKbgP3gMUT7suGU29awGIIQUDX 3tFZVZ6UU86YP3g4iuqO66fFHn5/gBBrSot2Tt+HLEMdhgRTy/doiuDCuMkOubyCb50W 1BMA== MIME-Version: 1.0 X-Received: by 10.50.122.104 with SMTP id lr8mr1826275igb.4.1397615376898; Tue, 15 Apr 2014 19:29:36 -0700 (PDT) Received: by 10.64.168.72 with HTTP; Tue, 15 Apr 2014 19:29:36 -0700 (PDT) In-Reply-To: References: <1394222924-28886-1-git-send-email-yinghai@kernel.org> <20140408025738.GA3198@yanx> <20140409075215.GA3173@yanx> <20140415115450.GA7792@yanx> Date: Tue, 15 Apr 2014 19:29:36 -0700 X-Google-Sender-Auth: Q5rjhndAmJbgwou5MOYRv_AxRYM Message-ID: Subject: Re: [PATCH v7] PCI: Try best to allocate pref mmio 64bit above 4g From: Yinghai Lu To: Bjorn Helgaas Cc: Guo Chao , Benjamin Herrenschmidt , Wei Yang , Gavin Shan , Jack Morgenstein , Amir Vadai , Or Gerlitz , Eugenia Emantayev , talal@mellanox.com, "linux-pci@vger.kernel.org" Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,RP_MATCHES_RCVD,T_DKIM_INVALID,T_TVD_MIME_EPI, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Tue, Apr 15, 2014 at 5:09 PM, Bjorn Helgaas wrote: >> It went wrong at the beginning. Note the error message never considers >> 64-bit or not, but BAR 15 here has it MEM_64 flag cleared. > > BAR 15 is a bridge window. I think its resource flags should reflect > the capability of the *window*, even if we disable the window or we > happen to assign addresses that are under 4GB. So I think it's wrong > that we clear the MEM_64 flag in pbus_size_mem() and the IO flag in > pbus_size_io(). We keep PCI_PREF_RANGE_TYPE_64 in the flag. We should check that before we touch PCI_PREF_LIMIT_UPPER32 BAR in pci_setup_bridge_mmio_pref() like following: Subject: [PATCH] PCI: only touch upper 32bit for pref64bit bridge bar If the bridge pref mmio bar does not support 64bit, we should touch upper 32bit. Signed-off-by: Yinghai Lu --- drivers/pci/setup-bus.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) Subject: [PATCH] PCI: only touch upper 32bit for pref64bit bridge bar If the bridge pref mmio bar does not support 64bit, we should touch upper 32bit. Signed-off-by: Yinghai Lu --- drivers/pci/setup-bus.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) Index: linux-2.6/drivers/pci/setup-bus.c =================================================================== --- linux-2.6.orig/drivers/pci/setup-bus.c +++ linux-2.6/drivers/pci/setup-bus.c @@ -592,23 +592,23 @@ static void pci_setup_bridge_mmio(struct static void pci_setup_bridge_mmio_pref(struct pci_bus *bus) { struct pci_dev *bridge = bus->self; - struct resource *res; + struct resource *res = bus->resource[2]; struct pci_bus_region region; u32 l, bu, lu; /* Clear out the upper 32 bits of PREF limit. If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily disables PREF range, which is ok. */ - pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0); + if (res->flags & PCI_PREF_RANGE_TYPE_64) + pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0); /* Set up PREF base/limit. */ bu = lu = 0; - res = bus->resource[2]; pcibios_resource_to_bus(bridge->bus, ®ion, res); if (res->flags & IORESOURCE_PREFETCH) { l = (region.start >> 16) & 0xfff0; l |= region.end & 0xfff00000; - if (res->flags & IORESOURCE_MEM_64) { + if (res->flags & PCI_PREF_RANGE_TYPE_64) { bu = upper_32_bits(region.start); lu = upper_32_bits(region.end); } @@ -619,8 +619,10 @@ static void pci_setup_bridge_mmio_pref(s pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l); /* Set the upper 32 bits of PREF base & limit. */ - pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu); - pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu); + if (res->flags & PCI_PREF_RANGE_TYPE_64) { + pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu); + pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu); + } } static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type)