From patchwork Thu Nov 21 20:18:39 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yinghai Lu X-Patchwork-Id: 3220681 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 6DC5E9F461 for ; Thu, 21 Nov 2013 20:18:44 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7A2F42077F for ; Thu, 21 Nov 2013 20:18:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9F2B52076C for ; Thu, 21 Nov 2013 20:18:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752537Ab3KUUSl (ORCPT ); Thu, 21 Nov 2013 15:18:41 -0500 Received: from mail-ie0-f176.google.com ([209.85.223.176]:64796 "EHLO mail-ie0-f176.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752079Ab3KUUSl (ORCPT ); Thu, 21 Nov 2013 15:18:41 -0500 Received: by mail-ie0-f176.google.com with SMTP id at1so478778iec.7 for ; Thu, 21 Nov 2013 12:18:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:sender:in-reply-to:references:date:message-id:subject :from:to:cc:content-type; bh=qiQPbFKw6m03RX1dj4x76Qt70faxAzmODjWc8C/LZtA=; b=Pi69oMDDRffuP4hW/cZIRyPMmaiVgLZOb8VsX5DnC+pch4IM771jXh3B2V6oxuDWyK NapkuSWx+AKiqJ0r06XQyM3Xr9027GmoEAE1OSlwai5RppAHwoCRlTb6G6rUzn3vKQBG Cg1ykbDpAcjuR2MneM3g78jTQOMrYbilHKqM61QNPCoMxaJkrh0TsW0LrGxa9AQESWXP r4aXBtkKLy4p399kL9bEaNwVDzyuSnd+VYPgDCyBHDZwAtQ7thIBHWLU0QSlXqhY3sSf KgrINpuJIZBqYBHtodF2E4ZO0azN5qpL/IyeBBQ4qNRjhfJcI1Gns+wsW+jxutTmDvhm Cr/g== MIME-Version: 1.0 X-Received: by 10.50.16.45 with SMTP id c13mr28841720igd.55.1385065120391; Thu, 21 Nov 2013 12:18:40 -0800 (PST) Received: by 10.64.235.70 with HTTP; Thu, 21 Nov 2013 12:18:39 -0800 (PST) In-Reply-To: <20131121103021.GA29873@yanx> References: <1384912317-3721-1-git-send-email-yinghai@kernel.org> <1384912317-3721-7-git-send-email-yinghai@kernel.org> <20131121103021.GA29873@yanx> Date: Thu, 21 Nov 2013 12:18:39 -0800 X-Google-Sender-Auth: 0QQgsNxhPDNfiJaz0zTnQiNUrAo Message-ID: Subject: Re: [PATCH 6/6] PCI: Try to allocate mem64 above 4G at first From: Yinghai Lu To: Guo Chao , Bjorn Helgaas , Linus Torvalds Cc: "linux-pci@vger.kernel.org" Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-7.3 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,RP_MATCHES_RCVD,T_DKIM_INVALID,T_TVD_MIME_EPI, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Thu, Nov 21, 2013 at 2:30 AM, Guo Chao wrote: > Hi: > > On Tue, Nov 19, 2013 at 05:51:57PM -0800, Yinghai Lu wrote: >> Will fall back to below 4g if it can not find any above 4g. >> > > > > >> x86 32bit without X86_PAE support will have bottom set to 0, because >> resource_size_t is 32bit. >> >> Also for 32bit with resource_size_t 64bit kernel on machine with pae support >> we are safe because iomem_resource is limited to 32bit according to >> x86_phys_bits. >> >> -v2: update bottom assigning to make it clear for non-pae support machine. >> -v3: Bjorn's change: >> use MAX_RESOURCE instead of -1 >> use start/end instead of bottom/max >> for all arch instead of just x86_64 >> -v4: updated after PCI_MAX_RESOURCE_32 change. >> -v5: restore io handling to use PCI_MAX_RESOURCE_32 as limit. >> -v6: checking pcibios_resource_to_bus return for every bus res, to decide it >> if we need to try high at first. >> It supports all arches instead of just x86_64. >> > Work fine in our systems if '[RFC PATCH 3/3] PCI: do not reset bridge's > IORESOURCE_MEM_64 flag for ROM BAR' applied. > > Otherwise, in one system, the 32-bit window is too small to provide > fallback space for prefetchable windows of root bridge, causing all > prefethable resources failed to get addresses. > > Any comments about that patch? no, that patch is not right. That could prevent rom BAR getting allocate under 4G. solution could be: 1. Just remove pref on rom bar allocation. as attached rom_no_pref.patch 2. or treat pref rom as option resource, as attached rom_option_1_xxx.patch 3. or more generic, treat all pci BAR 32bit prefetechable as normal MMIO32 during allocation. aka mmio prefectechable will be used for pci bridge that support 64bit mmio pref and leave bridge's 32bit only pref bar register blank. Bjorn, Linus, Are you happy with No 3? Thanks Yinghai Subject: [PATCH] PCI: Treat ROM resource as optional during assigning. So will try to allocate them together with requested ones, if can not assign them, could go with requested one only, and just skip ROM resource. Signed-off-by: Yinghai Lu --- drivers/pci/setup-bus.c | 21 +++++++-------------- 1 file changed, 7 insertions(+), 14 deletions(-) Index: linux-2.6/drivers/pci/setup-bus.c =================================================================== --- linux-2.6.orig/drivers/pci/setup-bus.c +++ linux-2.6/drivers/pci/setup-bus.c @@ -303,18 +303,10 @@ static void assign_requested_resources_s idx = pci_dev_resource_idx(dev_res->dev, res); if (resource_size(res) && pci_assign_resource_fit(dev_res->dev, idx, fit)) { - if (fail_head) { - /* - * if the failed res is for ROM BAR, and it will - * be enabled later, don't add it to the list - */ - if (!((idx == PCI_ROM_RESOURCE) && - (!(res->flags & IORESOURCE_ROM_ENABLE)))) - add_to_list(fail_head, - dev_res->dev, res, - 0 /* don't care */, - 0 /* don't care */); - } + if (fail_head) + add_to_list(fail_head, dev_res->dev, res, + 0 /* don't care */, + 0 /* don't care */); reset_resource(res); } } @@ -903,8 +895,9 @@ static int pbus_size_mem(struct pci_bus continue; r_size = resource_size(r); - /* put SRIOV requested res to the optional list */ - if (realloc_head && is_pci_iov_resource_idx(i)) { + /* put SRIOV/ROM requested res to the optional list */ + if (realloc_head && (is_pci_iov_resource_idx(i) || + is_pci_rom_resource_idx(i))) { r->end = r->start - 1; add_to_list(realloc_head, dev, r, r_size, 0/* dont' care */); children_add_size += r_size;