From patchwork Wed Dec 25 08:27:58 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Emmanuel Grumbach X-Patchwork-Id: 3405351 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id C08F89F314 for ; Wed, 25 Dec 2013 08:28:04 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DC6822013A for ; Wed, 25 Dec 2013 08:28:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1D23520134 for ; Wed, 25 Dec 2013 08:28:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751288Ab3LYI2B (ORCPT ); Wed, 25 Dec 2013 03:28:01 -0500 Received: from mail-lb0-f169.google.com ([209.85.217.169]:57032 "EHLO mail-lb0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751246Ab3LYI2A (ORCPT ); Wed, 25 Dec 2013 03:28:00 -0500 Received: by mail-lb0-f169.google.com with SMTP id u14so3197563lbd.14 for ; Wed, 25 Dec 2013 00:27:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=GUCdGuzLB2/emQfm3iC5RjCBpr0QREJu/wvKVjuSBiw=; b=UE0BAHBo9bPRDjLjVlTeMZ51h2u3H3czI7ENDcCS/sWn4vPkXmXVm6QvPmLA6UpAh0 h8KHBTJXXKMOrHtQUuk1AfEAEUn1gBtfm6eewocnBPPpAbMKxaujDC4ybeBU7vQB+pgB E3bMm7wXd/m0rwkBNMZdhk6PUBIkcasIUendWyWwWUE/1PVPNkAkX1ZeOafiWdxfeFfy rugmje0FAQSWE1s3BpAl//gxvyAufizgvBTWTY7fWVWFa1dVE1thjk6S0v8WEDWMAQJI rdAXJjc8gYnWTFQ7+0RWhj6hiZPP4km0dAJAyrKanIzwhiUAWFIRYBhBHgYY30Hs2LUi e88A== MIME-Version: 1.0 X-Received: by 10.112.139.35 with SMTP id qv3mr457839lbb.47.1387960078342; Wed, 25 Dec 2013 00:27:58 -0800 (PST) Received: by 10.114.200.82 with HTTP; Wed, 25 Dec 2013 00:27:58 -0800 (PST) In-Reply-To: References: <0BA3FCBA62E2DC44AF3030971E174FB301DEA052@HASMSX103.ger.corp.intel.com> <52828364.6080103@gmail.com> <0BA3FCBA62E2DC44AF3030971E174FB301E02E49@HASMSX103.ger.corp.intel.com> <0BA3FCBA62E2DC44AF3030971E174FB301E02EC1@HASMSX103.ger.corp.intel.com> <0BA3FCBA62E2DC44AF3030971E174FB301E02FC6@HASMSX103.ger.corp.intel.com> <5285E028.20906@gmail.com> Date: Wed, 25 Dec 2013 10:27:58 +0200 Message-ID: Subject: Re: [Ilw] Intel Wireless 7260 hardware timed out randomly From: Emmanuel Grumbach To: wzyboy Cc: Bjorn Helgaas , "Grumbach, Emmanuel" , "ilw@linux.intel.com" , "linux-wireless@vger.kernel.org" , "linux-pci@vger.kernel.org" , "Bj?rn Mork" Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Fri, Nov 15, 2013 at 11:04 AM, wzyboy wrote: > Thanks a lot for explaination, Emmanuel! > > Now I finally know why this is a "catch-22" situation: Disabling those > features with OS/drvier cannot be as neat as disabling them directly > in BIOS. And there may be chance, that disabling them at a bad timing > may cause G3... > > -- Back to you. Can you please try not to do the setpci and add this: APMG_PCIDEV_STT_VAL_L1_ACT_DIS); thanks --- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/net/wireless/iwlwifi/pcie/tx.c b/drivers/net/wireless/iwlwifi/pcie/tx.c index 079a511..e8a52f3 100644 --- a/drivers/net/wireless/iwlwifi/pcie/tx.c +++ b/drivers/net/wireless/iwlwifi/pcie/tx.c @@ -707,6 +707,8 @@ void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr) iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG, reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); + iwl_set_bits_prph(trans, 0xa04068, 0x8); + /* Enable L1-Active */ iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,