From patchwork Thu Apr 10 21:56:00 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Greatorex X-Patchwork-Id: 3964941 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 20D3CBFF02 for ; Thu, 10 Apr 2014 21:56:12 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2619020829 for ; Thu, 10 Apr 2014 21:56:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E57BE2081D for ; Thu, 10 Apr 2014 21:56:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753800AbaDJV4I (ORCPT ); Thu, 10 Apr 2014 17:56:08 -0400 Received: from mail-we0-f181.google.com ([74.125.82.181]:37393 "EHLO mail-we0-f181.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753657AbaDJV4H (ORCPT ); Thu, 10 Apr 2014 17:56:07 -0400 Received: by mail-we0-f181.google.com with SMTP id q58so4590870wes.12 for ; Thu, 10 Apr 2014 14:56:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fatboyfat.co.uk; s=google; h=date:from:to:cc:subject:in-reply-to:message-id:references :user-agent:mime-version:content-type; bh=UuCdQ0ckQnmyKBUhWyBh6i/CqGa0+P4lKHpWfZT6FVs=; b=QlkeiyBcB3B6CSGAMCUEpc0EYQbxtZqR3Pi6SktSlHU7uPjdqwLug+voRNGLsljm/X CLoKOy62yxBwe7Wp+U0Fwuj7WNZ09ziu3Vv/xmBRk4Sk5Th+Aa0Mcnr5JeMHuv8VA2fs DuAlJUy3LfSIh755vChkmGlX6A8imCRBPO5R4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:date:from:to:cc:subject:in-reply-to:message-id :references:user-agent:mime-version:content-type; bh=UuCdQ0ckQnmyKBUhWyBh6i/CqGa0+P4lKHpWfZT6FVs=; b=f1l9WUCfYlG0hT2V4sVPWDOzarzdyOdAaCu7GQ0W36183K/HTdBgOvkUcPYae8y9Mp uI3gjud96wJSBut6gGP7Hc9MiIgaPb92KLn69wB9M1NNuDFRIJiMLvBIHFS/uhnGFxrv ATld9CFqiKOWcDGsr2dBBJ6f8z7JGScvnfw4V4RZBXf8m807Vr10QMEsVHbl2uv1BY8i fCOLIG1Q3JINSWfeGAsrM5eq4R0Ts4MfzhI5oBodzTmIXHTNMIVIcC2srRQvaK/WckrX hAk/vEesPeBjKaIKdXdNDpL74y0HzcvmO0b4kIFH9KvUNvRD0oTJsEus6Tkuestxiuz1 x5Nw== X-Gm-Message-State: ALoCoQl753ts5CPUGsX6FzAnxHQBAdoL3Xv3gWQpTZizF3zY2ovHFFeR9CPU3ng9nvZD7sDKlXW5 X-Received: by 10.194.161.168 with SMTP id xt8mr17287322wjb.35.1397166966133; Thu, 10 Apr 2014 14:56:06 -0700 (PDT) Received: from [2001:470:1f09:284::1b9d] ([2001:470:1f09:284::1b9d]) by mx.google.com with ESMTPSA id co9sm8335126wjb.22.2014.04.10.14.56.04 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 10 Apr 2014 14:56:04 -0700 (PDT) Date: Thu, 10 Apr 2014 22:56:00 +0100 (BST) From: Neil Greatorex X-X-Sender: neil@vroombuntu To: Jason Gunthorpe cc: Thomas Petazzoni , Willy Tarreau , Matthew Minter , Gerlando Falauto , linux-arm-kernel@lists.infradead.org, Jason Cooper , =?ISO-8859-15?Q?Gregory_Cl=E9ment?= , Ezequiel Garcia , Andrew Lunn , linux-pci@vger.kernel.org, Tawfik Bayouk , Lior Amsalem Subject: Re: Fixing PCIe issues on Armada XP In-Reply-To: <20140410201201.GA12661@obsidianresearch.com> Message-ID: References: <20140410181953.50ccfcc3@skate> <20140410165733.GB23104@obsidianresearch.com> <20140410200153.46669e0c@skate> <20140410201201.GA12661@obsidianresearch.com> User-Agent: Alpine 2.10 (DEB 1266 2009-07-14) MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-7.3 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,RP_MATCHES_RCVD,T_DKIM_INVALID,T_TVD_MIME_EPI, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Jason, On Thu, 10 Apr 2014, Jason Gunthorpe wrote: > Gating the clock without disabling the Phy first does sound like a > bad idea.. > > Neil, does this do anything for you? > > diff --git a/arch/arm/mach-mvebu/mvebu-soc-id.c b/arch/arm/mach-mvebu/mvebu-soc-id.c > index f3b325f..e0a032f 100644 > --- a/arch/arm/mach-mvebu/mvebu-soc-id.c > +++ b/arch/arm/mach-mvebu/mvebu-soc-id.c > @@ -107,7 +107,7 @@ static int __init mvebu_soc_id_init(void) > iounmap(pci_base); > > res_ioremap: > - clk_disable_unprepare(clk); > +// clk_disable_unprepare(clk); > > clk_err: > of_node_put(child); > That patch has fixed it for me. The PCIe card seems to be now be always properly detected. > In any event, turning on the clock should almost certainly be > accompanied by a phy reset sequence to get both link ends on the same > page. > > Attached is a rough, untested patch along those lines. > I took your attached patch and extended it a bit to print out how long it took. The delays also need to be much longer for me. I also fixed a small typo you made where the bit wasn't being set again to bring the link back up. I've attached the diff to your patch, as well as the combined patch (hope that makes sense). With the attached patch I get the following output: mirabox ~ # dmesg | grep PCIe0.0 [ 0.135947] mvebu-pcie pcie-controller.3: PCIe0.0: performing link reset [ 0.161989] mvebu-pcie pcie-controller.3: PCIe0.0: link went down after 26 tries [ 0.173984] mvebu-pcie pcie-controller.3: PCIe0.0: link came back up after 12 tries mirabox ~ # lspci 00:01.0 PCI bridge: Marvell Technology Group Ltd. Device 6710 (rev 01) 00:02.0 PCI bridge: Marvell Technology Group Ltd. Device 6710 (rev 01) 01:00.0 Ethernet controller: Intel Corporation I350 Gigabit Network Connection (rev 01) 01:00.1 Ethernet controller: Intel Corporation I350 Gigabit Network Connection (rev 01) 03:00.0 USB controller: Fresco Logic FL1009 USB 3.0 Host Controller (rev 02) So that seems to also work. I will leave it to you and Thomas to decide which approach is better! Cheers, Neil diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c index c902ca0..d09a7e5 100644 --- a/drivers/pci/host/pci-mvebu.c +++ b/drivers/pci/host/pci-mvebu.c @@ -1054,15 +1054,25 @@ static int mvebu_pcie_probe(struct platform_device *pdev) mvebu_writel(port, reg & ~BIT(30), // Conf_TrainingDisable PCIE_CTRL_OFF); - do { - udelay(100); // Guess? - } while (mvebu_pcie_link_up(port)); + + for (tries = 0; + mvebu_pcie_link_up(port) && tries < 100; tries++) + mdelay(1); + + dev_info(&pdev->dev, + "PCIe%d.%d: link went down after %d tries\n", + port->port, port->lane, tries); + mvebu_pcie_set_local_dev_nr(port, 1); - mvebu_writel(port, reg | ~BIT(30), PCIE_CTRL_OFF); + mvebu_writel(port, reg | BIT(30), PCIE_CTRL_OFF); for (tries = 0; !mvebu_pcie_link_up(port) && tries != 100; tries++) - udelay(100); + mdelay(1); + + dev_info(&pdev->dev, + "PCIe%d.%d: link came back up after %d tries\n", + port->port, port->lane, tries); } else { /* We expect the bootloader has setup the port and * waited for the link to go up