From patchwork Fri Jul 21 02:32:45 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Honghui Zhang X-Patchwork-Id: 9855899 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8CABB600F5 for ; Fri, 21 Jul 2017 02:33:39 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 79A9120410 for ; Fri, 21 Jul 2017 02:33:39 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6E65920499; Fri, 21 Jul 2017 02:33:39 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0A8F920410 for ; Fri, 21 Jul 2017 02:33:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S966381AbdGUCdK (ORCPT ); Thu, 20 Jul 2017 22:33:10 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:62838 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S966251AbdGUCdB (ORCPT ); Thu, 20 Jul 2017 22:33:01 -0400 Received: from mtkcas09.mediatek.inc [(172.21.101.178)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 82825529; Fri, 21 Jul 2017 10:32:55 +0800 Received: from mtkexhb01.mediatek.inc (172.21.101.102) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Fri, 21 Jul 2017 10:32:54 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkexhb01.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Fri, 21 Jul 2017 10:32:54 +0800 From: To: , , , , , , , , , , CC: , , , , , , Subject: [PATCH 3/5] dt-bindings: PCI: rename and cleanup MediaTek binding text Date: Fri, 21 Jul 2017 10:32:45 +0800 Message-ID: X-Mailer: git-send-email 2.6.4 In-Reply-To: References: MIME-Version: 1.0 X-MTK: N Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Ryder Lee In order to accommodate other SoC generations, this patch updates filename to make it more generic, regroups specific properties by SoCs, and removes redundant descriptions. Signed-off-by: Ryder Lee --- ...{mediatek,mt7623-pcie.txt => mediatek-pcie.txt} | 29 +++++++++++----------- 1 file changed, 14 insertions(+), 15 deletions(-) rename Documentation/devicetree/bindings/pci/{mediatek,mt7623-pcie.txt => mediatek-pcie.txt} (91%) diff --git a/Documentation/devicetree/bindings/pci/mediatek,mt7623-pcie.txt b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt similarity index 91% rename from Documentation/devicetree/bindings/pci/mediatek,mt7623-pcie.txt rename to Documentation/devicetree/bindings/pci/mediatek-pcie.txt index fe80dda..294f4a3 100644 --- a/Documentation/devicetree/bindings/pci/mediatek,mt7623-pcie.txt +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt @@ -1,18 +1,13 @@ -MediaTek Gen2 PCIe controller which is available on MT7623 series SoCs - -PCIe subsys supports single root complex (RC) with 3 Root Ports. Each root -ports supports a Gen2 1-lane Link and has PIPE interface to PHY. +MediaTek Gen2 PCIe controller Required properties: -- compatible: Should contain "mediatek,mt7623-pcie". +- compatible: Should contain one of the following string: + "mediatek,mt7623-pcie" + "mediatek,mt2701-pcie" - device_type: Must be "pci" - reg: Base addresses and lengths of the PCIe controller. - #address-cells: Address representation for root ports (must be 3) - #size-cells: Size representation for root ports (must be 2) -- #interrupt-cells: Size representation for interrupts (must be 1) -- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties - Please refer to the standard PCI bus binding document for a more detailed - explanation. - clocks: Must contain an entry for each entry in clock-names. See ../clocks/clock-bindings.txt for details. - clock-names: Must include the following entries: @@ -20,12 +15,6 @@ Required properties: - sys_ck0 :for clock of Port0 - sys_ck1 :for clock of Port1 - sys_ck2 :for clock of Port2 -- resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names: Must include the following entries: - - pcie-rst0 :port0 reset - - pcie-rst1 :port1 reset - - pcie-rst2 :port2 reset - phys: List of PHY specifiers (used by generic PHY framework). - phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the number of PHYs as specified in *phys* property. @@ -34,6 +23,16 @@ Required properties: - bus-range: Range of bus numbers associated with this controller. - ranges: Ranges for the PCI memory and I/O regions. +Required properties for MT7623/MT2701: +- #interrupt-cells: Size representation for interrupts (must be 1) +- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties + Please refer to the standard PCI bus binding document for a more detailed + explanation. +- resets: Must contain an entry for each entry in reset-names. + See ../reset/reset.txt for details. +- reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the + number of root ports. + In addition, the device tree node must have sub-nodes describing each PCIe port interface, having the following mandatory properties: