From patchwork Thu Dec 12 11:38:45 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagannadha Sutradharudu Teki X-Patchwork-Id: 3331511 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 134B19F37A for ; Thu, 12 Dec 2013 11:40:01 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B2C6C2041D for ; Thu, 12 Dec 2013 11:39:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CFFDB207D7 for ; Thu, 12 Dec 2013 11:39:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751624Ab3LLLjK (ORCPT ); Thu, 12 Dec 2013 06:39:10 -0500 Received: from ch1ehsobe002.messaging.microsoft.com ([216.32.181.182]:25403 "EHLO ch1outboundpool.messaging.microsoft.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751492Ab3LLLi7 (ORCPT ); Thu, 12 Dec 2013 06:38:59 -0500 Received: from mail209-ch1-R.bigfish.com (10.43.68.242) by CH1EHSOBE017.bigfish.com (10.43.70.67) with Microsoft SMTP Server id 14.1.225.22; Thu, 12 Dec 2013 11:38:58 +0000 Received: from mail209-ch1 (localhost [127.0.0.1]) by mail209-ch1-R.bigfish.com (Postfix) with ESMTP id BDC03360B65; Thu, 12 Dec 2013 11:38:58 +0000 (UTC) X-Forefront-Antispam-Report: CIP:149.199.60.83; KIP:(null); UIP:(null); IPV:NLI; H:xsj-gw1; RD:unknown-60-83.xilinx.com; EFVD:NLI X-SpamScore: -3 X-BigFish: VPS-3(zzbb2dId799hzz1f42h2148h208ch1ee6h1de0h1fdah2073h2146h1202h1e76h2189h1d1ah1d2ah1fc6hzz1de098h17326ah8275bh1de097h186068h5eeeKz2fh95h839hd24hf0ah119dh1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h14ddh1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1b0ah224fh1d0ch1d2eh1d3fh1dfeh1dffh1e1dh1e23h1fe8h1ff5h2218h2216h226dh2327h2336h906i1155h) Received-SPF: pass (mail209-ch1: domain of xilinx.com designates 149.199.60.83 as permitted sender) client-ip=149.199.60.83; envelope-from=jagannadha.sutradharudu-teki@xilinx.com; helo=xsj-gw1 ; helo=xsj-gw1 ; Received: from mail209-ch1 (localhost.localdomain [127.0.0.1]) by mail209-ch1 (MessageSwitch) id 1386848336201380_31816; Thu, 12 Dec 2013 11:38:56 +0000 (UTC) Received: from CH1EHSMHS035.bigfish.com (snatpool1.int.messaging.microsoft.com [10.43.68.246]) by mail209-ch1.bigfish.com (Postfix) with ESMTP id 21EFF42021C; Thu, 12 Dec 2013 11:38:56 +0000 (UTC) Received: from xsj-gw1 (149.199.60.83) by CH1EHSMHS035.bigfish.com (10.43.70.35) with Microsoft SMTP Server id 14.16.227.3; Thu, 12 Dec 2013 11:38:55 +0000 Received: from unknown-38-66.xilinx.com ([149.199.38.66] helo=xsj-smtp1) by xsj-gw1 with esmtp (Exim 4.63) (envelope-from ) id 1Vr4bX-0005wC-Gv; Thu, 12 Dec 2013 03:38:55 -0800 From: Jagannadha Sutradharudu Teki To: Bjorn Helgaas CC: Rob Landley , , , , Jagannadha Sutradharudu Teki Subject: [PATCH v2 2/2] Documentation: pci: Add pcie-howto.txt Date: Thu, 12 Dec 2013 17:08:45 +0530 X-Mailer: git-send-email 1.8.3 In-Reply-To: <1386848325-21064-1-git-send-email-jaganna@xilinx.com> References: <1386848325-21064-1-git-send-email-jaganna@xilinx.com> X-RCIS-Action: ALLOW MIME-Version: 1.0 Message-ID: X-OriginatorOrg: xilinx.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Added pcie-howto.txt for describing the information on PCI Express basics and Root Complex driver. Signed-off-by: Jagannadha Sutradharudu Teki --- Changes for v2: - Fixed comments from "Randy Dunlap" Documentation/PCI/00-INDEX | 2 + Documentation/PCI/pcie-howto.txt | 186 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 188 insertions(+) create mode 100644 Documentation/PCI/pcie-howto.txt diff --git a/Documentation/PCI/00-INDEX b/Documentation/PCI/00-INDEX index b8b7721..d61e7b9 100644 --- a/Documentation/PCI/00-INDEX +++ b/Documentation/PCI/00-INDEX @@ -6,6 +6,8 @@ pci-error-recovery.txt - Info on PCI error recovery MSI-HOWTO.txt - The Message Signaled Interrupts (MSI) Driver Guide HOWTO and FAQ +pcie-howto.txt + - A guide describing the PCI Express basics and Root Complex driver pcie-portbus-howto.txt - A guide describing the PCI Express Port Bus driver pcie-aer-howto.txt diff --git a/Documentation/PCI/pcie-howto.txt b/Documentation/PCI/pcie-howto.txt new file mode 100644 index 0000000..df464b5 --- /dev/null +++ b/Documentation/PCI/pcie-howto.txt @@ -0,0 +1,186 @@ + PCI Express HOWTO + Jagannadha Sutradharudu Teki + 12/12/2013 + +1. About this guide + +This guide describes the basics of the PCI Express bus and provides +information on what the Linux PCIe subsystem looks like and ends with +a brief description of PCI Host controller/Root complex driver along +with some sample code. + +2. Basic terminology and conventions + +PCI Express is +- A high performance IO interconnect for peripherals. +- Low hardware design overhead compared to PCI, as it uses less pins. +- A serial point-to-point interconnect between two devices. +- Implements packet-based protocol for data transfer. +- Supports features like Advanced power management, Advanced error + reporting facility, and hot-plug. + _________ + | | + | CPU | + |_________| + | + ___________________|___________________________ + | | ________ + | ROOT COMPLEX | | | + | |--------| Memory | + | Switch Port Root port | |________| + |_______________________________________________| + | PCIe Bus0 + ____________________________|______________________________________ + | | | + ____ ______|______ | ____|____ + | | / \ __|__ | | + | EP |-----| SWITCH | | | | BRIDGE | + |____| \_____________/ | EP | | PCIe - | + | | |_____| | PCI/PCIe| + __|__ __|__ |_________| + | | | | | PCIe Bus1 + | EP | | EP | __________|________________ + |_____| |_____| | | + __|__ __|__ + | | | | + | EP | | EP | + |_____| |_____| + +Root Complex (RC) +Connects the CPU and memory subsystem to the PCIe fabric (A topology comprised of PCIe +nodes like Root Complex, Endpoint, Bridge or a Switch) + +Port +Interface between a PCIe component and the Link. + +Link +PCIe interconnect is referred as a Link, and connects two devices. + +Lane +A PCIe link consists of either 1, 2, 4, 8, 12, 16 or 32 signals in each direction +(each signal needs two wires - one for Tx and other for Rx). These signals are +referred to as Lanes. + +Upstream Port +Port that points in the direction of RC. + +Downstream Port +Port that points away from the RC. + +Root Port +Whose upstream port is RC and dowstream port should be an EP or Bridge. + +Switch Port +Whose upstream port is RC and dowstream port is always a switch. + +Endpoint (EP) +Devices other than RC, Switches and Bridges which either generate or terminate a PCIe +transaction. These are peripheral devices such as Ethernet, USB and graphics devices. + +Switch +PCIe device single upstream port as RC and multiple downstream ports as EP's, +Switches or Bridges. + +Bridge +Is for extending PCIe Bus segment - whose downstream port points to one more PCIe bus. + +3. Linux PCIe Subsystem + + ifconfig open()/close/read()/write() /proc, /sys + ^ ^ ^ ^ + | | | | + | | | | + | | | V + | | | PCIe Port Bus services + | | | (AER, HP, PME, VC + | | | drivers/pci/pcie/ + | | | drivers/pci/hotplug) + V V V ^ + Socket Block Char | + layer Subsystem Subsystem | + ^ ^ ^ | pcie_port_service_register() + | | | | + | | | | + V V V V + Common net USB Input PCIe Port Core + device layer Core Core (drivers/pci/pcie/portdrv_core.c) + ^ ^ ^ ^ + | | | | pcie_port_bus_register() + | | | | + _____V_____ ____V____ ____V_____ _________V___________ + | | | | | | | | + All these are | GEM | | USB HC | | Mouse/KB/| | PCIe Port Bus driver| + PCI endpoint | Controller| | driver | | TS HC | | (drivers/pci/pcie/ | + drivers | driver | | | | driver | | portdrv_pci.c) | + |___________| |_________| |__________| |_____________________| + ^ ^ ^ ^ + |__________ | | _________| + | | | | pci_register_driver() + ___________________ pci_bus_*() __V___V_____________V__________V______ + | | pci_scan_root_bus() | | + | PCI BIOS |-------------------->| PCI Core | + | (arch/arm/kernel/ |<--------------------| (drivers/pci/pci* | + ----->| bios32.c)) |<--- pcibios_*() | drivers/pci/bus.c) | + | |___________________| | |______________________________________| + | ^ | + | | | pci_common_init_dev() + | | | + ____V___ ____V___ ___V____ + | | | | | | + | Renesas| | Tegra | | Exynos | + | PCI HC | | PCIe HC| | PCIe HC| drivers/pci/host/ + | driver | | driver | | driver | All these are + |________| |________| |________| PCI Root Complex drivers + | | | + | | | + V V V + platform_driver_register() + +Note: +Linux PCI subsystem is like above one without having a PCIe port bus stack. +For more details about this block see http://jagannadhteki.blog.com/2013/12/04/linux-pcie-subsystem/ + +PCI HC/RC driver +- Low level initialization and configuration (board, SoC) +- Invokes PCI-BIOS - for bus enumerations so that the endpoints on bus are ready. +- Supplies struct pci_ops to read/write config space. +- Setup the resources like bus numbers, memory/IO space, Interrupt numbers, MSI. +- Register PCI-BIOS as pci_common_init_dev() + +PCI BIOS +- Architecture specific PCI +- Bus enumeration - Lane, Bus, Device, Memory, Interrupt. +- Successful completion of BIOS assures that all the endpoints in bus are + assigned parts of available PCI resources and their respective Endpoint drivers + can take control of them using the functionalities provided by PCI Core. +- Register to PCI core for common accessing of endpoint drivers. +- pci_scan_root_bus() and pci_bus_*() + +PCI Core +- Provides services to Lower level BIOS and Upper level endpoint layers. +- Creates device entries for proc/sysfs information. +- Linux kernel PCI bus and driver management code. +- Provides set of abstraction functions that endpoint drivers can use to + initiate PCI communication with attached endpoints. +- Calls BIOS codes with pcibios_* + +PCI Endpoint driver +- Individual endpoint drivers from upper layer. +- Accessing config space upon respective endpoint enumeration done. +- Communicate over the endpoint for Tx/Rx transactions. +- Register to PCI core as pci_driver_register() + +PCIe Port Bus driver +- A logical PCI-PCI Bridge structure. +- Root Port and the Switch Port. +- See Documentation/PCI/pcie-portbus-howto.txt + +4. PCI HC/RC driver + +4.1 Description + +4.2 Sample code + +5. References +http://www.mindshare.com/files/ebooks/pci%20express%20system%20architecture.pdf +http://www.pcisig.com/developers/main/training_materials/