From patchwork Mon Oct 29 07:01:21 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush ANAND X-Patchwork-Id: 1661471 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id 79A91DFB7A for ; Mon, 29 Oct 2012 07:02:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752636Ab2J2HCX (ORCPT ); Mon, 29 Oct 2012 03:02:23 -0400 Received: from eu1sys200aog102.obsmtp.com ([207.126.144.113]:52221 "EHLO eu1sys200aog102.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752432Ab2J2HCW (ORCPT ); Mon, 29 Oct 2012 03:02:22 -0400 Received: from beta.dmz-ap.st.com ([138.198.100.35]) (using TLSv1) by eu1sys200aob102.postini.com ([207.126.147.11]) with SMTP ID DSNKUI4p9MxJBdIEC0vJoZlg6l5X1XKmUUxG@postini.com; Mon, 29 Oct 2012 07:02:21 UTC Received: from zeta.dmz-ap.st.com (ns6.st.com [138.198.234.13]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id BA49F141; Mon, 29 Oct 2012 06:53:56 +0000 (GMT) Received: from Webmail-ap.st.com (eapex1hubcas2.st.com [10.80.176.10]) by zeta.dmz-ap.st.com (STMicroelectronics) with ESMTP id A0F3E988; Mon, 29 Oct 2012 07:02:09 +0000 (GMT) Received: from localhost (10.199.81.103) by Webmail-ap.st.com (10.80.176.7) with Microsoft SMTP Server (TLS) id 8.3.245.1; Mon, 29 Oct 2012 15:02:09 +0800 From: Pratyush Anand To: , , Cc: , , , , Pratyush Anand Subject: [PATCH 07/15] SPEAr1340: Add PCIe auxdata for miphy clock initialization Date: Mon, 29 Oct 2012 12:31:21 +0530 Message-ID: X-Mailer: git-send-email 1.7.5.4 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Miphy Clock initialization is very specific to controller and its instances. Pass this custom function using auxdata. Signed-off-by: Pratyush Anand --- arch/arm/mach-spear13xx/spear1340.c | 26 ++++++++++++++++++++++++++ 1 files changed, 26 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-spear13xx/spear1340.c b/arch/arm/mach-spear13xx/spear1340.c index 223d9ef..194c3ac 100644 --- a/arch/arm/mach-spear13xx/spear1340.c +++ b/arch/arm/mach-spear13xx/spear1340.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include @@ -42,6 +43,7 @@ #define SPEAR1340_CAM2_BASE UL(0xD0400000) #define SPEAR1340_CAM3_BASE UL(0xD0500000) #define SPEAR1340_SATA_BASE UL(0xB1000000) +#define SPEAR1340_PCIE_BASE UL(0xB1000000) #define SPEAR1340_UART1_BASE UL(0xB4100000) #define SPEAR1340_I2S_PLAY_BASE UL(0xB2400000) #define SPEAR1340_I2S_REC_BASE UL(0xB2000000) @@ -358,6 +360,28 @@ static struct ahci_platform_data sata_pdata = { .resume = sata_resume, }; +static int spear1340_pcie_clk_init(struct pcie_port *pp) +{ + writel(SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE, + SPEAR1340_PCIE_MIPHY_CFG); + writel(SPEAR1340_PCIE_CFG_VAL, SPEAR1340_PCIE_SATA_CFG); + + return 0; +} + +static int spear1340_pcie_clk_exit(struct pcie_port *pp) +{ + writel(0, SPEAR1340_PCIE_SATA_CFG); + writel(0, SPEAR1340_PCIE_MIPHY_CFG); + + return 0; +} + +static struct pcie_port_info pcie_pdata = { + .clk_init = spear1340_pcie_clk_init, + .clk_exit = spear1340_pcie_clk_exit, +}; + /* camera sensor registeration */ static struct i2c_board_info vs6725_camera_sensor_info = { I2C_BOARD_INFO("vs6725", 0x10), @@ -609,6 +633,8 @@ static struct of_dev_auxdata spear1340_auxdata_lookup[] __initdata = { OF_DEV_AUXDATA("snps,spear-ahci", SPEAR1340_SATA_BASE, NULL, &sata_pdata), + OF_DEV_AUXDATA("st,pcie-host", SPEAR1340_PCIE_BASE, NULL, + &pcie_pdata), OF_DEV_AUXDATA("arm,pl011", SPEAR1340_UART1_BASE, NULL, &uart1_data), OF_DEV_AUXDATA("st,spear600-gmac", SPEAR13XX_GETH_BASE, NULL, ð_data),