From patchwork Sun Sep 8 17:32:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Kiszka X-Patchwork-Id: 13795579 Received: from mta-65-226.siemens.flowmailer.net (mta-65-226.siemens.flowmailer.net [185.136.65.226]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 864C0171E65 for ; Sun, 8 Sep 2024 17:32:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.136.65.226 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725816770; cv=none; b=e4Q/SmTIENFH+3mC+wYs7o8eAlaULdoLYK0O44ab7WfyDdc6nbNAxwChMuT3I2gWaZqJTSgWFD9rpPlSVBqJxl8u97z39+DpNgnHEIycACz+x7PZVS6J8CNVH+gB6/UcnmOk226prKrHc/4wNOLe+u4Ycg1rHoG05R7IWP/TPzw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725816770; c=relaxed/simple; bh=8DZAIx78tX09RUB958aT4rufSeZEMPqRli6/uDdiQJw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=eUdZ4naDUMCnX1vSkUBnBhAaAGB+GRMy+iBteS5mek2zDXLjkTXqhavMReDqBaay05YzpwKGSWti9bMi2k+pHjaLvXV6fk+iJ25iiZjPSma2IdZn09ylhturWJfSZSylZ/NMzpPOtcUrKo4icLfaUSsPjxBCJgt1zIME80j0EAE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=siemens.com; spf=pass smtp.mailfrom=rts-flowmailer.siemens.com; dkim=pass (2048-bit key) header.d=siemens.com header.i=jan.kiszka@siemens.com header.b=LoKs2TnZ; arc=none smtp.client-ip=185.136.65.226 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=siemens.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rts-flowmailer.siemens.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=siemens.com header.i=jan.kiszka@siemens.com header.b="LoKs2TnZ" Received: by mta-65-226.siemens.flowmailer.net with ESMTPSA id 202409081732390014f2b7fc8bcd469f for ; Sun, 08 Sep 2024 19:32:39 +0200 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=fm1; d=siemens.com; i=jan.kiszka@siemens.com; h=Date:From:Subject:To:Message-ID:MIME-Version:Content-Type:Content-Transfer-Encoding:Cc:References:In-Reply-To; bh=iFfd2t0Dq0yUbDlytZqHUfYp4qV0roKUDvsOPNNJEZ0=; b=LoKs2TnZzLXdjszaU1pSG3Bnko+QVRi/hrJJmm5YVDXgFTeJrEr9bgBNLlWvrNEDw0Qgk7 JRKPhlsKuO4ToDf4DfYAiUkww8qjWPZiaKsne9pKQec/7ByBPlsHJf5iFRghS1rXgAFvQDop 2RnbSOrT2a9OuPKX8c4rVJktnlYMnshIf7oSq3rWbV25w3Wz3YbapdZnpgewhQlvdiVVRn5I ZmF6jk7csaA93FMD/BVa//7W+arhlbmgfRYtJpa/AniwE0ydghoraOaxxL6VdgYT2xsHjEfL Ks2l3qzAvPtlDTHaObzpHvxplnIJe+MTiC6YrXzT1+qSpkWDCGASMhSg==; From: Jan Kiszka To: Nishanth Menon , Santosh Shilimkar , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, Siddharth Vadapalli , Bao Cheng Su , Hua Qian Li , Diogo Ivo Subject: [PATCH v5 7/7] arm64: dts: ti: iot2050: Add overlay for DMA isolation for devices behind PCI RC Date: Sun, 8 Sep 2024 19:32:33 +0200 Message-ID: In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Flowmailer-Platform: Siemens Feedback-ID: 519:519-294854:519-21489:flowmailer From: Jan Kiszka Reserve a 64M memory region and ensure that all PCI devices do their DMA only inside that region. This is configured via a restricted-dma-pool and enforced with the help of the first PVU. Applying this isolation is not totally free in terms of overhead and memory consumption. It makes only sense for variants that support secure booting, and generally only when this is actually enable. Therefore model it as overlay that can be activated on demand. The firmware will take care of this via DT fixup during boot and will also provide a way to adjust the pool size. Signed-off-by: Jan Kiszka --- arch/arm64/boot/dts/ti/Makefile | 5 +++ ...am6548-iot2050-advanced-dma-isolation.dtso | 33 +++++++++++++++++++ 2 files changed, 38 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-dma-isolation.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index bcd392c3206e..b6ee943be8c6 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -74,8 +74,10 @@ k3-am654-gp-evm-dtbs := k3-am654-base-board.dtb \ k3-am654-evm-dtbs := k3-am654-base-board.dtb k3-am654-icssg2.dtbo k3-am654-idk-dtbs := k3-am654-evm.dtb k3-am654-idk.dtbo k3-am654-pcie-usb2.dtbo k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-dtbs := k3-am6548-iot2050-advanced-m2.dtb \ + k3-am6548-iot2050-advanced-dma-isolation.dtbo \ k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie.dtbo k3-am6548-iot2050-advanced-m2-bkey-usb3-dtbs := k3-am6548-iot2050-advanced-m2.dtb \ + k3-am6548-iot2050-advanced-dma-isolation.dtbo \ k3-am6548-iot2050-advanced-m2-bkey-usb3.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am6528-iot2050-basic.dtb dtb-$(CONFIG_ARCH_K3) += k3-am6528-iot2050-basic-pg2.dtb @@ -240,7 +242,10 @@ DTC_FLAGS_k3-am62p5-sk += -@ DTC_FLAGS_k3-am642-evm += -@ DTC_FLAGS_k3-am642-phyboard-electra-rdk += -@ DTC_FLAGS_k3-am642-tqma64xxl-mbax4xxl += -@ +DTC_FLAGS_k3-am6548-iot2050-advanced += -@ DTC_FLAGS_k3-am6548-iot2050-advanced-m2 += -@ +DTC_FLAGS_k3-am6548-iot2050-advanced-pg2 += -@ +DTC_FLAGS_k3-am6548-iot2050-advanced-sm += -@ DTC_FLAGS_k3-am68-sk-base-board += -@ DTC_FLAGS_k3-am69-sk += -@ DTC_FLAGS_k3-j721e-common-proc-board += -@ diff --git a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-dma-isolation.dtso b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-dma-isolation.dtso new file mode 100644 index 000000000000..dfd75d2dc245 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-dma-isolation.dtso @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IOT2050, overlay for isolating DMA requests via PVU + * Copyright (c) Siemens AG, 2024 + * + * Authors: + * Jan Kiszka + */ + +/dts-v1/; +/plugin/; + +&{/reserved-memory} { + #address-cells = <2>; + #size-cells = <2>; + + pci_restricted_dma_region: restricted-dma@c0000000 { + compatible = "restricted-dma-pool"; + reg = <0 0xc0000000 0 0x4000000>; + }; +}; + +&pcie0_rc { + memory-region = <&pci_restricted_dma_region>; +}; + +&pcie1_rc { + memory-region = <&pci_restricted_dma_region>; +}; + +&ti_pvu0 { + status = "okay"; +};