From patchwork Fri Jun 21 14:48:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13707726 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C87C6631; Fri, 21 Jun 2024 14:49:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718981369; cv=none; b=BdQMpB+3IUb7knaZtH36pjHVAn0hFs24MBU0frWX1YyvnO40ZffVki8n4Dk74sOriiAGG3yKJdddcmz7GAhHSqf+oGsEslfuqjorpAp11xklnG3DPdIOf/JAOsVXLRmZGDOFdQZ5csSzcTsGme9yfQ1qGyBeUA6zU6QGnoqvZFc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718981369; c=relaxed/simple; bh=Zf8oDaaRN4fc057eHxK8XWV3Bfsxm5d5LDYfo3qGYHE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=R3OP2SoC8dZOTg0jccklrxVm8K3nHrgQG+aI6CsSWiqigVWkuW2b8S8y0yr3COMDrntPwCFqidVeTUeEqKEC4KVZLhGabGR9XnpKdWETp3NVd3yDNwGRqBxR5yqWv+rmLSHzoknr+iN/E+6NFCAudCvEMTCpS1rzQ50VWVTjCKM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=lMxhzbIo; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="lMxhzbIo" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C65A0C2BBFC; Fri, 21 Jun 2024 14:49:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1718981369; bh=Zf8oDaaRN4fc057eHxK8XWV3Bfsxm5d5LDYfo3qGYHE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lMxhzbIoz84mA+lEL2oLRJeGSOfPaoH/U/RG1WOMrCl7swDx6H+RxDcSrfrC8IHaE DyoFJi8ZlDJMHatr5XGqgPDNB42mzHhQqO43XIHl1QHfm8b5QIJTnocvdG+Cgzvqfw sr7kZim6NEYblFGmOZIDEy6HF6IGlJZK5yJDX3TMTEX9aYGsZgEHM/BnGkJWAElM38 PVnFDKZet8WtvhL+iiqxle7r35FGMrXEHBVf1oqDN/fB+HdoBgH+Mvo6yzgi+XSxLH PX92+UzY94FEVJmzlc8pU6SzLNfD2I/4etaqiHjZIiIJ2hfyK6O7VS4ygrJ1U2AywU J/zn/imC0VtyA== From: Lorenzo Bianconi To: linux-pci@vger.kernel.org Cc: ryder.lee@mediatek.com, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, linux-mediatek@lists.infradead.org, lorenzo.bianconi83@gmail.com, linux-arm-kernel@lists.infradead.org, krzysztof.kozlowski+dt@linaro.org, devicetree@vger.kernel.org, nbd@nbd.name, dd@embedd.com, upstream@airoha.com, angelogioacchino.delregno@collabora.com Subject: [PATCH 4/4] PCI: mediatek-gen3: Add Airoha EN7581 support Date: Fri, 21 Jun 2024 16:48:50 +0200 Message-ID: X-Mailer: git-send-email 2.45.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Introduce support for Airoha EN7581 pcie controller to mediatek-gen3 pcie controller driver. Tested-by: Zhengping Zhang Signed-off-by: Lorenzo Bianconi --- drivers/pci/controller/Kconfig | 2 +- drivers/pci/controller/pcie-mediatek-gen3.c | 84 ++++++++++++++++++++- 2 files changed, 84 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig index e534c02ee34f..3bd6c9430010 100644 --- a/drivers/pci/controller/Kconfig +++ b/drivers/pci/controller/Kconfig @@ -196,7 +196,7 @@ config PCIE_MEDIATEK config PCIE_MEDIATEK_GEN3 tristate "MediaTek Gen3 PCIe controller" - depends on ARCH_MEDIATEK || COMPILE_TEST + depends on ARCH_AIROHA || ARCH_MEDIATEK || COMPILE_TEST depends on PCI_MSI help Adds support for PCIe Gen3 MAC controller for MediaTek SoCs. diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c index 9842617795a9..2dacfed665c6 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -7,6 +7,7 @@ */ #include +#include #include #include #include @@ -21,6 +22,8 @@ #include #include #include +#include +#include #include "../pci.h" @@ -29,6 +32,7 @@ #define PCI_CLASS(class) (class << 8) #define PCIE_RC_MODE BIT(0) +#define PCIE_EQ_PRESET_01_REF 0x100 #define PCIE_CFGNUM_REG 0x140 #define PCIE_CFG_DEVFN(devfn) ((devfn) & GENMASK(7, 0)) #define PCIE_CFG_BUS(bus) (((bus) << 8) & GENMASK(15, 8)) @@ -68,6 +72,7 @@ #define PCIE_MSI_SET_ENABLE_REG 0x190 #define PCIE_MSI_SET_ENABLE GENMASK(PCIE_MSI_SET_NUM - 1, 0) +#define PCIE_PIPE4_PIE8_REG 0x338 #define PCIE_MSI_SET_BASE_REG 0xc00 #define PCIE_MSI_SET_OFFSET 0x10 #define PCIE_MSI_SET_STATUS_OFFSET 0x04 @@ -100,7 +105,7 @@ #define PCIE_ATR_TLP_TYPE_MEM PCIE_ATR_TLP_TYPE(0) #define PCIE_ATR_TLP_TYPE_IO PCIE_ATR_TLP_TYPE(2) -#define MAX_NUM_PHY_RSTS 1 +#define MAX_NUM_PHY_RSTS 3 struct mtk_gen3_pcie; @@ -848,6 +853,72 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie) return 0; } +static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) +{ + struct device *dev = pcie->dev; + int err; + + writel_relaxed(0x23020133, pcie->base + 0x10044); + writel_relaxed(0x50500032, pcie->base + 0x15030); + writel_relaxed(0x50500032, pcie->base + 0x15130); + + err = phy_init(pcie->phy); + if (err) { + dev_err(dev, "failed to initialize PHY\n"); + return err; + } + mdelay(30); + + err = phy_power_on(pcie->phy); + if (err) { + dev_err(dev, "failed to power on PHY\n"); + goto err_phy_on; + } + + err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_rsts, + pcie->phy_resets); + if (err) { + dev_err(dev, "failed to deassert PHYs\n"); + goto err_phy_deassert; + } + usleep_range(5000, 10000); + + pm_runtime_enable(dev); + pm_runtime_get_sync(dev); + + err = clk_bulk_prepare(pcie->num_clks, pcie->clks); + if (err) { + dev_err(dev, "failed to prepare clock\n"); + goto err_clk_prepare; + } + + writel_relaxed(0x41474147, pcie->base + PCIE_EQ_PRESET_01_REF); + writel_relaxed(0x1018020f, pcie->base + PCIE_PIPE4_PIE8_REG); + mdelay(10); + + err = clk_bulk_enable(pcie->num_clks, pcie->clks); + if (err) { + dev_err(dev, "failed to prepare clock\n"); + goto err_clk_enable; + } + + return 0; + +err_clk_enable: + clk_bulk_unprepare(pcie->num_clks, pcie->clks); +err_clk_prepare: + pm_runtime_put_sync(dev); + pm_runtime_disable(dev); + reset_control_bulk_assert(pcie->soc->phy_resets.num_rsts, + pcie->phy_resets); +err_phy_deassert: + phy_power_off(pcie->phy); +err_phy_on: + phy_exit(pcie->phy); + + return err; +} + static int mtk_pcie_power_up(struct mtk_gen3_pcie *pcie) { struct device *dev = pcie->dev; @@ -1117,8 +1188,19 @@ static const struct mtk_pcie_soc mtk_pcie_soc_mt8192 = { }, }; +static const struct mtk_pcie_soc mtk_pcie_soc_en7581 = { + .power_up = mtk_pcie_en7581_power_up, + .phy_resets = { + .id[0] = "phy-lane0", + .id[1] = "phy-lane1", + .id[2] = "phy-lane2", + .num_rsts = 3, + }, +}; + static const struct of_device_id mtk_pcie_of_match[] = { { .compatible = "mediatek,mt8192-pcie", .data = &mtk_pcie_soc_mt8192 }, + { .compatible = "airoha,en7581-pcie", .data = &mtk_pcie_soc_en7581 }, {}, }; MODULE_DEVICE_TABLE(of, mtk_pcie_of_match);