From patchwork Wed Mar 29 11:29:03 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Gonzalez X-Patchwork-Id: 9651379 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 63B4A602C8 for ; Wed, 29 Mar 2017 11:37:15 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4A9A420499 for ; Wed, 29 Mar 2017 11:37:15 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3F5CD27CAF; Wed, 29 Mar 2017 11:37:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 972CF20499 for ; Wed, 29 Mar 2017 11:37:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756037AbdC2LgD (ORCPT ); Wed, 29 Mar 2017 07:36:03 -0400 Received: from mail1.bemta8.messagelabs.com ([216.82.243.207]:36367 "EHLO mail1.bemta8.messagelabs.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755967AbdC2Lf1 (ORCPT ); Wed, 29 Mar 2017 07:35:27 -0400 Received: from [216.82.241.100] by server-15.bemta-8.messagelabs.com id 22/55-01669-CFB9BD85; Wed, 29 Mar 2017 11:35:24 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrLIsWRWlGSWpSXmKPExsVy+LrFKt3fs29 HGNzcqWOxY+lmJov5R86xWrw6s5bNYtPja6wWl3fNYbM4O+84m8WBpe0sFm9+v2C3+HvnH5vF wQ9PWC1ans5gtNi8aSqzA49H/+wpbB5r5q1h9Ohf95nVY9OqTjaPd+fOsXtsXlLv8XmTXAB7F GtmXlJ+RQJrRsvFs+wF53QrDiz+x9LAuE69i5GLQ0hgGaPEhKUNbF2MnBzCArYSjfvOMoLYbA ImEjfvn2MBsUUEiiS+v5rDCtLALHCYWWLPpevsIAkhAWeJ7y0/wZp5geyTX/6CxVkEVCXerpz GBGKLCiRIXPwzhRWiRlDi5MwnYEM5BVwkLh0/BbaMWUBfomnrHGYIW15i+1sIW0hAW+L9xsVg vRICChJTJ7cyT2Dkn4Vk1Cwk7bOQtC9gZF7FqF6cWlSWWqRrqZdUlJmeUZKbmJmja2hgoZebW lycmJ6ak5hUrJecn7uJERgtDECwg3HdVOdDjJIcTEqivCcMb0cI8SXlp1RmJBZnxBeV5qQWH2 KU4eBQkuA9MgsoJ1iUmp5akZaZA4xbmLQEB4+SCO9PkDRvcUFibnFmOkTqFKOilDjvL5CEAEg iozQPrg2WKi4xykoJ8zICHSLEU5BalJtZgir/ilGcg1FJmHcGyBSezLwSuOmvgBYzAS0Wt7kF srgkESEl1cDoEhE9pzqs9fMTX/dFn33OXVCo+t287G6LslRdOePJumkW3+sceqR3W8nUS4V4W 6tu8Hoy87ZKwcOFaTf3TT0jp+NrUHbilRNDoZ1x72XZBwLdSbPvZ/uuUl5tVpSy9NLH+xe+PH xl4//j5/mzKgU5UbYs6h6PH2Ww8PPV9N5YtfSLwlF1y81KLMUZiYZazEXFiQAKOOmkEAMAAA= = X-Env-Sender: Marc_Gonzalez@sigmadesigns.com X-Msg-Ref: server-13.tower-220.messagelabs.com!1490787322!165306866!1 X-Originating-IP: [195.215.56.170] X-StarScan-Received: X-StarScan-Version: 9.2.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 4967 invoked from network); 29 Mar 2017 11:35:23 -0000 Received: from 195-215-56-170-static.dk.customer.tdc.net (HELO CPH-EX1.SDESIGNS.COM) (195.215.56.170) by server-13.tower-220.messagelabs.com with AES128-SHA encrypted SMTP; 29 Mar 2017 11:35:23 -0000 Received: from [172.27.0.114] (172.27.0.114) by CPH-EX1.sdesigns.com (192.168.10.36) with Microsoft SMTP Server (TLS) id 14.3.294.0; Wed, 29 Mar 2017 13:35:22 +0200 Subject: [PATCH v3 1/2] PCI: Add tango MSI controller support From: Marc Gonzalez To: Bjorn Helgaas , Marc Zyngier , Thomas Gleixner CC: Robin Murphy , Lorenzo Pieralisi , Liviu Dudau , David Laight , linux-pci , Linux ARM , Thibaud Cornic , Phuong Nguyen , LKML , DT , Mason References: <5309e718-5813-5b79-db57-9d702b50d0f9@sigmadesigns.com> Message-ID: Date: Wed, 29 Mar 2017 13:29:03 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:51.0) Gecko/20100101 Firefox/51.0 SeaMonkey/2.48 MIME-Version: 1.0 In-Reply-To: <5309e718-5813-5b79-db57-9d702b50d0f9@sigmadesigns.com> X-Originating-IP: [172.27.0.114] Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The MSI controller in Tango supports 256 message-signaled interrupts, and a single doorbell address. Signed-off-by: Marc Gonzalez --- Changes since v0.2 - Support 256 MSIs instead of only 32 - Use spinlock_t instead of struct mutex - Add MSI_FLAG_PCI_MSIX flag IRQs are acked in tango_msi_isr because handle_simple_irq leaves ack, clear, mask and unmask up to the driver. For the same reason, interrupt enable mask is updated from tango_irq_domain_alloc/free. --- drivers/pci/host/pcie-tango.c | 194 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 194 insertions(+) diff --git a/drivers/pci/host/pcie-tango.c b/drivers/pci/host/pcie-tango.c new file mode 100644 index 000000000000..e88850983a1d --- /dev/null +++ b/drivers/pci/host/pcie-tango.c @@ -0,0 +1,194 @@ +#include +#include +#include +#include +#include + +#define MSI_MAX 256 + +struct tango_pcie { + DECLARE_BITMAP(bitmap, MSI_MAX); + spinlock_t lock; + void __iomem *mux; + void __iomem *msi_status; + void __iomem *msi_mask; + phys_addr_t msi_doorbell; + struct irq_domain *irq_domain; + struct irq_domain *msi_domain; + int irq; +}; + +/*** MSI CONTROLLER SUPPORT ***/ + +static void dispatch(struct tango_pcie *pcie, unsigned long status, int base) +{ + unsigned int pos, virq; + + for_each_set_bit(pos, &status, 32) { + virq = irq_find_mapping(pcie->irq_domain, base + pos); + generic_handle_irq(virq); + } +} + +static void tango_msi_isr(struct irq_desc *desc) +{ + u32 status; + struct irq_chip *chip = irq_desc_get_chip(desc); + struct tango_pcie *pcie = irq_desc_get_handler_data(desc); + unsigned int base, offset, pos = 0; + + chained_irq_enter(chip, desc); + + while ((pos = find_next_bit(pcie->bitmap, MSI_MAX, pos)) < MSI_MAX) { + base = round_down(pos, 32); + offset = (pos / 32) * 4; + status = readl_relaxed(pcie->msi_status + offset); + writel_relaxed(status, pcie->msi_status + offset); + dispatch(pcie, status, base); + pos = base + 32; + } + + chained_irq_exit(chip, desc); +} + +static struct irq_chip tango_msi_irq_chip = { + .name = "MSI", + .irq_mask = pci_msi_mask_irq, + .irq_unmask = pci_msi_unmask_irq, +}; + +#define USE_DEF_OPS (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS) + +static struct msi_domain_info msi_domain_info = { + .flags = USE_DEF_OPS | MSI_FLAG_PCI_MSIX, + .chip = &tango_msi_irq_chip, +}; + +static void tango_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) +{ + struct tango_pcie *pcie = irq_data_get_irq_chip_data(data); + + msg->address_lo = lower_32_bits(pcie->msi_doorbell); + msg->address_hi = upper_32_bits(pcie->msi_doorbell); + msg->data = data->hwirq; +} + +static int tango_set_affinity(struct irq_data *irq_data, + const struct cpumask *mask, bool force) +{ + return -EINVAL; +} + +static struct irq_chip tango_msi_chip = { + .name = "MSI", + .irq_compose_msi_msg = tango_compose_msi_msg, + .irq_set_affinity = tango_set_affinity, +}; + +static int find_free_msi(struct irq_domain *dom, unsigned int virq) +{ + u32 val; + struct tango_pcie *pcie = dom->host_data; + unsigned int offset, pos; + + pos = find_first_zero_bit(pcie->bitmap, MSI_MAX); + if (pos >= MSI_MAX) + return -ENOSPC; + + offset = (pos / 32) * 4; + val = readl_relaxed(pcie->msi_mask + offset); + writel_relaxed(val | BIT(pos % 32), pcie->msi_mask + offset); + __set_bit(pos, pcie->bitmap); + + irq_domain_set_info(dom, virq, pos, &tango_msi_chip, + dom->host_data, handle_simple_irq, NULL, NULL); + + return 0; +} + +static int tango_irq_domain_alloc(struct irq_domain *dom, + unsigned int virq, unsigned int nr_irqs, void *args) +{ + int err; + struct tango_pcie *pcie = dom->host_data; + + spin_lock(&pcie->lock); + err = find_free_msi(dom, virq); + spin_unlock(&pcie->lock); + + return err; +} + +static void tango_irq_domain_free(struct irq_domain *dom, + unsigned int virq, unsigned int nr_irqs) +{ + u32 val; + struct irq_data *d = irq_domain_get_irq_data(dom, virq); + struct tango_pcie *pcie = irq_data_get_irq_chip_data(d); + unsigned int offset, pos = d->hwirq; + + spin_lock(&pcie->lock); + + offset = (pos / 32) * 4; + val = readl_relaxed(pcie->msi_mask + offset); + writel_relaxed(val & ~BIT(pos % 32), pcie->msi_mask + offset); + __clear_bit(pos, pcie->bitmap); + + spin_unlock(&pcie->lock); +} + +static const struct irq_domain_ops msi_dom_ops = { + .alloc = tango_irq_domain_alloc, + .free = tango_irq_domain_free, +}; + +static int tango_msi_remove(struct platform_device *pdev) +{ + struct tango_pcie *msi = platform_get_drvdata(pdev); + + irq_set_chained_handler_and_data(msi->irq, NULL, NULL); + irq_domain_remove(msi->msi_domain); + irq_domain_remove(msi->irq_domain); + + return 0; +} + +static int tango_msi_probe(struct platform_device *pdev, struct tango_pcie *pcie) +{ + int i, virq; + struct fwnode_handle *fwnode = of_node_to_fwnode(pdev->dev.of_node); + struct irq_domain *msi_dom, *irq_dom; + + spin_lock_init(&pcie->lock); + + for (i = 0; i < MSI_MAX / 32; ++i) + writel_relaxed(0, pcie->msi_mask + i * 4); + + irq_dom = irq_domain_create_linear(fwnode, MSI_MAX, &msi_dom_ops, pcie); + if (!irq_dom) { + pr_err("Failed to create IRQ domain\n"); + return -ENOMEM; + } + + msi_dom = pci_msi_create_irq_domain(fwnode, &msi_domain_info, irq_dom); + if (!msi_dom) { + pr_err("Failed to create MSI domain\n"); + irq_domain_remove(irq_dom); + return -ENOMEM; + } + + virq = platform_get_irq(pdev, 1); + if (virq <= 0) { + pr_err("Failed to map IRQ\n"); + irq_domain_remove(msi_dom); + irq_domain_remove(irq_dom); + return -ENXIO; + } + + pcie->irq_domain = irq_dom; + pcie->msi_domain = msi_dom; + pcie->irq = virq; + irq_set_chained_handler_and_data(virq, tango_msi_isr, pcie); + + return 0; +}