From patchwork Wed Oct 1 08:09:28 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Takashi Iwai X-Patchwork-Id: 5010191 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 26B199F375 for ; Wed, 1 Oct 2014 08:09:35 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3155C20259 for ; Wed, 1 Oct 2014 08:09:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 18C872015D for ; Wed, 1 Oct 2014 08:09:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750987AbaJAIJc (ORCPT ); Wed, 1 Oct 2014 04:09:32 -0400 Received: from cantor2.suse.de ([195.135.220.15]:55038 "EHLO mx2.suse.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750846AbaJAIJ3 (ORCPT ); Wed, 1 Oct 2014 04:09:29 -0400 Received: from relay1.suse.de (charybdis-ext.suse.de [195.135.220.254]) by mx2.suse.de (Postfix) with ESMTP id 670F5AAF1; Wed, 1 Oct 2014 08:09:28 +0000 (UTC) Date: Wed, 01 Oct 2014 10:09:28 +0200 Message-ID: From: Takashi Iwai To: Benjamin Herrenschmidt Cc: Alex Deucher , Bjorn Helgaas , Dave Airlie , Brian King , linux-pci@vger.kernel.org, Yijing Wang , Anton Blanchard , linuxppc-dev@ozlabs.org Subject: Re: [PATCH 4/4] sounds/hda/radeon: Disable 64-bit DMA on radeon In-Reply-To: <1412149289.4285.204.camel@pasglop> References: <1412129393.4285.195.camel@pasglop> <1412149289.4285.204.camel@pasglop> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI/1.14.6 (Maruoka) FLIM/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL/10.8 Emacs/24.3 (x86_64-suse-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI 1.14.6 - "Maruoka") Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP At Wed, 01 Oct 2014 17:41:29 +1000, Benjamin Herrenschmidt wrote: > > On Wed, 2014-10-01 at 09:38 +0200, Takashi Iwai wrote: > > > > diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c > > > index 3e6d22d..2b679d5 100644 > > > --- a/sound/pci/hda/hda_intel.c > > > +++ b/sound/pci/hda/hda_intel.c > > > @@ -297,7 +297,7 @@ enum { > > > /* quirks for ATI/AMD HDMI */ > > > #define AZX_DCAPS_PRESET_ATI_HDMI \ > > > (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\ > > > - AZX_DCAPS_NO_MSI64) > > > + AZX_DCAPS_NO_MSI64 | AZX_DCAPS_NO_64BIT) > > > > The only concern is that this will disable 64bit DMA also on x86 where > > it has been working fine. Can we add an ifdef CONFIG_PPC for this? > > I don't like that approach because technically the chip doesn't do > 64-bit DMA ... it does something like 40 or 48 (might actually depend on > the chip version) and for all I know it will break on future x86 with > more memory or other platforms with similar address encodings as > powerpc... > > The right thing might be to get the exact number of bits and do the > appropriate dma_set_mask() like the graphics driver does, but that's a > bit tricky unless we add a DMA mask field in that big array of chips in > there... I think setting the dma mask explicitly would be a better approach although it results in a bit bigger change. At least, it would impact less than forcing 32bit DMA, as most desktop machines have less than 40bit address. How about a patch like below? Only compile tested, and feel free to add more tags or edit comments appropriately. (I'm on vacation now, so have little time to type :) thanks, Takashi --- From: Takashi Iwai Subject: [PATCH] ALSA: hda - Limit 40bit DMA for AMD HDMI controllers AMD/ATI HDMI controller chip models, we already have a filter to lower to 32bit DMA, but the rest are supposed to be working with 64bit although the hardware doesn't really work with 64bit but only with 40 or 48bit DMA. In this patch, we take 40bit DMA for safety for the AMD/ATI controllers as the graphics drivers does. Signed-off-by: Takashi Iwai --- sound/pci/hda/hda_intel.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c index aa302fb03fc5..6410a3edf8ff 100644 --- a/sound/pci/hda/hda_intel.c +++ b/sound/pci/hda/hda_intel.c @@ -1482,6 +1482,7 @@ static int azx_first_init(struct azx *chip) struct snd_card *card = chip->card; int err; unsigned short gcap; + unsigned int dma_bits = 64; #if BITS_PER_LONG != 64 /* Fix up base address on ULI M5461 */ @@ -1521,6 +1522,8 @@ static int azx_first_init(struct azx *chip) /* disable SB600 64bit support for safety */ if (chip->pci->vendor == PCI_VENDOR_ID_ATI) { struct pci_dev *p_smbus; + /* AMD devices support 40 or 48bit DMA, take the safe one */ + dma_bits = 40; p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, NULL); @@ -1550,9 +1553,11 @@ static int azx_first_init(struct azx *chip) } /* allow 64bit DMA address if supported by H/W */ - if ((gcap & AZX_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64))) - pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64)); - else { + if (!(gcap & AZX_GCAP_64OK)) + dma_bits = 32; + if (!pci_set_dma_mask(pci, DMA_BIT_MASK(dma_bits))) { + pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(dma_bits)); + } else { pci_set_dma_mask(pci, DMA_BIT_MASK(32)); pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32)); }