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Mon, 22 Feb 2021 05:23:34 -0600 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 22 Feb 2021 05:23:33 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 22 Feb 2021 05:23:33 -0600 Received: from a0393678-ssd.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 11MBNFDZ088010; Mon, 22 Feb 2021 05:23:17 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Peter Rosin , Swapnil Jakhade Subject: [PATCH v2 0/9] AM64: Add SERDES bindings and driver support Date: Mon, 22 Feb 2021 16:53:05 +0530 Message-ID: <20210222112314.10772-1-kishon@ti.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210222_062355_560087_E4699163 X-CRM114-Status: GOOD ( 13.75 ) X-Mailman-Approved-At: Mon, 22 Feb 2021 22:59:48 -0500 X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org AM64 uses the same SERDES as in J7200, however AM642 EVM doesn't have a clock generator (unlike J7200 base board). Here the clock from the SERDES has to be routed to the PCIE connector. This series adds support to drive reference clock output from SERDES and also adds SERDES (torrent) and SERDES wrapper (WIZ) bindings. v1 of the patch series can be found @ [1] Changes from v1: *) Model the internal clocks without device tree input (Add #clock-cells to SERDES DT nodes for getting a reference to the clock using index to phandle). This is in accordance with comment given by Rob [2]. However the existing method to model clocks from device tree is not removed to support upstreamed device tree. *) Included a patch to fix modifying static data by instance specific initializations. *) Added a fix to delete "clk_div_sel" clk provider during cleanup [1] -> https://lore.kernel.org/r/20201224114250.1083-1-kishon@ti.com [2] -> http://lore.kernel.org/r/20210108025943.GA1790601@robh.at.kernel.org Kishon Vijay Abraham I (9): dt-bindings: phy: ti,phy-j721e-wiz: Add bindings for AM64 SERDES Wrapper dt-bindings: phy: cadence-torrent: Add binding for refclk driver dt-bindings: ti-serdes-mux: Add defines for AM64 SoC phy: ti: j721e-wiz: Remove "regmap_field" from wiz_clk_{mux|div}_sel phy: ti: j721e-wiz: Delete "clk_div_sel" clk provider during cleanup phy: ti: j721e-wiz: Configure full rate divider for AM64 phy: ti: j721e-wiz: Model the internal clocks without device tree input phy: ti: j721e-wiz: Enable reference clock output in cmn_refclk_

phy: cadence-torrent: Add support to drive refclk out .../bindings/phy/phy-cadence-torrent.yaml | 20 +- .../bindings/phy/ti,phy-j721e-wiz.yaml | 10 +- drivers/phy/cadence/phy-cadence-torrent.c | 202 +++++++++- drivers/phy/ti/phy-j721e-wiz.c | 349 +++++++++++++++--- include/dt-bindings/mux/ti-serdes.h | 5 + include/dt-bindings/phy/phy-cadence-torrent.h | 2 + include/dt-bindings/phy/phy-ti.h | 21 ++ 7 files changed, 553 insertions(+), 56 deletions(-) create mode 100644 include/dt-bindings/phy/phy-ti.h