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[83.51.243.231]) by smtp.gmail.com with ESMTPSA id u5sm3642433wrt.38.2021.05.06.04.15.33 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 May 2021 04:15:33 -0700 (PDT) From: Sergio Paracuellos To: vkoul@kernel.org Cc: linux-phy@lists.infradead.org, kishon@ti.com, robh+dt@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev, gregkh@linuxfoundation.org, neil@brown.name, ilya.lipnitskiy@gmail.com Subject: [PATCH 0/5] phy: ralink: mt7621-pci-phy: some improvements Date: Thu, 6 May 2021 13:15:26 +0200 Message-Id: <20210506111531.21978-1-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210506_041536_657830_93A970C5 X-CRM114-Status: GOOD ( 13.32 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Hi all, This series contains some improvements in the pci phy driver for MT7621 SoCs. MT7621 SoC clock driver has already mainlined in 'commit 48df7a26f470 ("clk: ralink: add clock driver for mt7621 SoC")' Because of this we can update schema documentation and device tree to add related clock entries and avoid custom architecture code in favour of using the clock kernel framework to retrieve clock frequency needed to properly configure the PCIe related Phys. After this changes there is no problem to properly enable this driver for COMPILE_TEST. Configuration has also modified from 'tristate' to 'bool' depending on PCI_MT7621 which seems to have more sense. Thanks in advance for your time. Best regards, Sergio Paracuellos Sergio Paracuellos (5): staging: mt7621-dts: use clock in pci phy nodes dt-bindings: phy: mediatek,mt7621-pci-phy: add clock entries phy: ralink: phy-mt7621-pci: use kernel clock APIS phy: ralink: Kconfig: enable COMPILE_TEST on mt7621-pci-phy driver phy: ralink: Kconfig: convert mt7621-pci-phy into 'bool' .../bindings/phy/mediatek,mt7621-pci-phy.yaml | 12 +++++++ drivers/phy/ralink/Kconfig | 4 +-- drivers/phy/ralink/phy-mt7621-pci.c | 33 +++++++++++-------- drivers/staging/mt7621-dts/mt7621.dtsi | 4 +++ 4 files changed, 38 insertions(+), 15 deletions(-)