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Wed, 28 Jul 2021 16:54:56 +0200 Received: from vleu-orange.cadence.com (10.160.88.83) by maileu3.global.cadence.com (10.160.88.99) with Microsoft SMTP Server (TLS) id 15.0.1497.2 via Frontend Transport; Wed, 28 Jul 2021 16:54:56 +0200 Received: from vleu-orange.cadence.com (localhost.localdomain [127.0.0.1]) by vleu-orange.cadence.com (8.14.4/8.14.4) with ESMTP id 16SEsuK3016331; Wed, 28 Jul 2021 16:54:56 +0200 Received: (from sjakhade@localhost) by vleu-orange.cadence.com (8.14.4/8.14.4/Submit) id 16SEssoP015985; Wed, 28 Jul 2021 16:54:54 +0200 From: Swapnil Jakhade To: , , , , CC: , , Subject: [PATCH v3 0/9] PHY: Prepare Cadence Torrent PHY driver to support multilink DP Date: Wed, 28 Jul 2021 16:54:45 +0200 Message-ID: <20210728145454.15945-1-sjakhade@cadence.com> X-Mailer: git-send-email 2.15.0 MIME-Version: 1.0 X-OrganizationHeadersPreserved: maileu3.global.cadence.com X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e92ace10-6dbf-426d-6b3e-08d951d7ac99 X-MS-TrafficTypeDiagnostic: BN0PR07MB8245: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8882; 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It also does the basic cleanup in order to add support for multilink DP configurations. The multilink DP series at [1] will be split in 2 parts and sent separately. This is part 1 of the series. Support for DP multilink configurations with register sequences will be added in part 2 as a separate patch series after validation. [1] https://lore.kernel.org/patchwork/cover/1410252/ Version History: v3: - Fixed register offset macro for PHY PCS lane registers in 9/9 v2: - Removed multilink DP support and register configuration patches - Fixed v1 review comments - Added Reviewed-by: Kishon Vijay Abraham I to patches 1/9, 3/9 and 7/9 Swapnil Jakhade (9): phy: cadence-torrent: Remove use of CamelCase to fix checkpatch CHECK message phy: cadence-torrent: Reorder few functions to remove function declarations phy: cadence-torrent: Add enum for supported input reference clock frequencies phy: cadence-torrent: Configure PHY registers as a function of input reference clock rate phy: cadence-torrent: Add PHY registers for DP in array format phy: cadence-torrent: Add PHY configuration for DP with 100MHz ref clock phy: cadence-torrent: Add separate functions for reusable code phy: cadence-torrent: Add debug information for PHY configuration phy: cadence-torrent: Check PIPE mode PHY status to be ready for operation drivers/phy/cadence/phy-cadence-torrent.c | 3181 ++++++++++++--------- 1 file changed, 1750 insertions(+), 1431 deletions(-)