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Wed, 8 Sep 2021 14:29:32 +0200 Received: from maileu3.global.cadence.com (10.160.88.99) by maileu4.global.cadence.com (10.160.110.201) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.2176.2; Wed, 8 Sep 2021 14:29:32 +0200 Received: from vleu-orange.cadence.com (10.160.88.83) by maileu3.global.cadence.com (10.160.88.99) with Microsoft SMTP Server (TLS) id 15.0.1497.2 via Frontend Transport; Wed, 8 Sep 2021 14:29:32 +0200 Received: from vleu-orange.cadence.com (localhost.localdomain [127.0.0.1]) by vleu-orange.cadence.com (8.14.4/8.14.4) with ESMTP id 188CTWEQ010267; Wed, 8 Sep 2021 14:29:32 +0200 Received: (from sjakhade@localhost) by vleu-orange.cadence.com (8.14.4/8.14.4/Submit) id 188CTU66010266; Wed, 8 Sep 2021 14:29:30 +0200 From: Swapnil Jakhade To: , , , , , , CC: , , , Subject: [PATCH v2 00/15] PHY: Add support for multilink configurations in Cadence Sierra PHY driver Date: Wed, 8 Sep 2021 14:29:15 +0200 Message-ID: <20210908122930.10224-1-sjakhade@cadence.com> X-Mailer: git-send-email 2.15.0 MIME-Version: 1.0 X-OrganizationHeadersPreserved: maileu3.global.cadence.com X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 307e26fa-1748-43bc-95bc-08d972c45189 X-MS-TrafficTypeDiagnostic: BN8PR07MB7025: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7691; 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This patch series extends functionality of Sierra PHY driver by adding features like support for multilink multiprotocol configurations, derived reference clock etc. The changes have been validated on TI J721E platform. Version History: v2: - Added a new patch 3/15 to rename the SSC macros for dt-bindings to use generic names. These macros are not yet used in any DTS file. Swapnil Jakhade (15): phy: cadence: Sierra: Use of_device_get_match_data() to get driver data phy: cadence: Sierra: Prepare driver to add support for multilink configurations dt-bindings: phy: cadence-torrent: Rename SSC macros to use generic names dt-bindings: phy: cadence-sierra: Add binding to specify SSC mode phy: cadence: Sierra: Add support to get SSC type from device tree phy: cadence: Sierra: Rename some regmap variables to be in sync with Sierra documentation phy: cadence: Sierra: Add PHY PCS common register configurations phy: cadence: Sierra: Check cmn_ready assertion during PHY power on phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operation phy: cadence: Sierra: Update single link PCIe register configuration phy: cadence: Sierra: Fix to get correct parent for mux clocks phy: cadence: Sierra: Add support for PHY multilink configurations phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configuration dt-bindings: phy: cadence-sierra: Add clock ID for derived reference clock phy: cadence: Sierra: Add support for derived reference clock output .../bindings/phy/phy-cadence-sierra.yaml | 9 + .../bindings/phy/phy-cadence-torrent.yaml | 4 +- drivers/phy/cadence/phy-cadence-sierra.c | 1299 +++++++++++++++-- include/dt-bindings/phy/phy-cadence.h | 9 +- 4 files changed, 1226 insertions(+), 95 deletions(-) Reviewed-by: Aswath Govindraju