| Message ID | 20220419010852.452169-1-victor.liu@nxp.com |
|---|---|
| Headers | show |
| Series | phy: phy-fsl-imx8-mipi-dphy: Add i.MX8qxp LVDS PHY mode support | expand |
On 19-04-22, 09:08, Liu Ying wrote: > Hi, > > This is the v8 series to add i.MX8qxp LVDS PHY mode support for the Mixel > PHY in the Freescale i.MX8qxp SoC. > > The Mixel PHY is MIPI DPHY + LVDS PHY combo, which can works in either > MIPI DPHY mode or LVDS PHY mode. The PHY mode is controlled by i.MX8qxp > SCU firmware. The PHY driver would call a SCU function to configure the > mode. > > The PHY driver is already supporting the Mixel MIPI DPHY in i.MX8mq SoC, > where it appears to be a single MIPI DPHY. > > > Patch 1/5 sets PHY mode in the Northwest Logic MIPI DSI host controller > bridge driver, since i.MX8qxp SoC embeds this controller IP to support > MIPI DSI displays together with the Mixel PHY. > > Patch 2/5 allows LVDS PHYs to be configured through the generic PHY functions > and through a custom structure added to the generic PHY configuration union. > > Patch 3/5 converts mixel,mipi-dsi-phy plain text dt binding to json-schema. > > Patch 4/5 adds dt binding support for the Mixel combo PHY in i.MX8qxp SoC. > > Patch 5/5 adds the i.MX8qxp LVDS PHY mode support in the Mixel PHY driver. Applied patch 2-5 to phy-next, thanks
On Wed, 2022-04-20 at 13:00 +0530, Vinod Koul wrote: > On 19-04-22, 09:08, Liu Ying wrote: > > Hi, > > > > This is the v8 series to add i.MX8qxp LVDS PHY mode support for the > > Mixel > > PHY in the Freescale i.MX8qxp SoC. > > > > The Mixel PHY is MIPI DPHY + LVDS PHY combo, which can works in > > either > > MIPI DPHY mode or LVDS PHY mode. The PHY mode is controlled by > > i.MX8qxp > > SCU firmware. The PHY driver would call a SCU function to > > configure the > > mode. > > > > The PHY driver is already supporting the Mixel MIPI DPHY in i.MX8mq > > SoC, > > where it appears to be a single MIPI DPHY. > > > > > > Patch 1/5 sets PHY mode in the Northwest Logic MIPI DSI host > > controller > > bridge driver, since i.MX8qxp SoC embeds this controller IP to > > support > > MIPI DSI displays together with the Mixel PHY. > > > > Patch 2/5 allows LVDS PHYs to be configured through the generic PHY > > functions > > and through a custom structure added to the generic PHY > > configuration union. > > > > Patch 3/5 converts mixel,mipi-dsi-phy plain text dt binding to > > json-schema. > > > > Patch 4/5 adds dt binding support for the Mixel combo PHY in > > i.MX8qxp SoC. > > > > Patch 5/5 adds the i.MX8qxp LVDS PHY mode support in the Mixel PHY > > driver. > > Applied patch 2-5 to phy-next, thanks Now that patch 2-5 landed in phy-next, patch 1 is needed to explicitly set MIPI DPHY mode in the nwl-dsi drm bridge driver, otherwise, i.MX8mq MIPI DSI display feature will be broken due to the phy mode check added in patch 5. I'm assuming patch 1 should go through drm-misc. Robert/drm folks, can you please pick it up? Thanks, Liu Ying
Hi, This is the v8 series to add i.MX8qxp LVDS PHY mode support for the Mixel PHY in the Freescale i.MX8qxp SoC. The Mixel PHY is MIPI DPHY + LVDS PHY combo, which can works in either MIPI DPHY mode or LVDS PHY mode. The PHY mode is controlled by i.MX8qxp SCU firmware. The PHY driver would call a SCU function to configure the mode. The PHY driver is already supporting the Mixel MIPI DPHY in i.MX8mq SoC, where it appears to be a single MIPI DPHY. Patch 1/5 sets PHY mode in the Northwest Logic MIPI DSI host controller bridge driver, since i.MX8qxp SoC embeds this controller IP to support MIPI DSI displays together with the Mixel PHY. Patch 2/5 allows LVDS PHYs to be configured through the generic PHY functions and through a custom structure added to the generic PHY configuration union. Patch 3/5 converts mixel,mipi-dsi-phy plain text dt binding to json-schema. Patch 4/5 adds dt binding support for the Mixel combo PHY in i.MX8qxp SoC. Patch 5/5 adds the i.MX8qxp LVDS PHY mode support in the Mixel PHY driver. Welcome comments, thanks. v7->v8: * Trivial kernel doc style fix for patch 2/5 - add '*'. * Resend with reviewer mail addresses updated for patch 1/5. v6->v7: * Update the year of copyright for patch 2/5. * Better variable explanation for bits_per_lane_and_dclk_cycle in patch 2/5. * Use marco instead of magic number for CCM and CA values for patch 5/5. * Suppress 'checkpatch --strict' warnings for patch 5/5. v5->v6: * Rebase the series upon v5.17-rc1. * Set PHY mode in ->mode_set() instead of ->pre_enable() in the nwl-dsi bridge driver in patch 1/5 due to the rebase. * Drop Guido's R-b tag on patch 1/5 due to the rebase. v4->v5: * Align kernel-doc style of include/linux/phy/phy-lvds.h to include/linux/phy/phy.h for patch 2/5. (Vinod) * Trivial tweaks on patch 2/5. * Drop Robert's R-b tag on patch 2/5. v3->v4: * Add all R-b tags received from v3 on relevant patches and respin. (Robert) v2->v3: * Improve readability of mixel_dphy_set_mode() in the Mixel PHY driver. (Guido) * Improve the 'clock-names' property in the PHY dt binding. v1->v2: * Convert mixel,mipi-dsi-phy plain text dt binding to json-schema. (Guido) * Print invalid PHY mode in dmesg from the Mixel PHY driver. (Guido) * Add Guido's R-b tag on the patch for the nwl-dsi drm bridge driver. Liu Ying (5): drm/bridge: nwl-dsi: Set PHY mode in nwl_dsi_mode_set() phy: Add LVDS configuration options dt-bindings: phy: Convert mixel,mipi-dsi-phy to json-schema dt-bindings: phy: mixel: mipi-dsi-phy: Add Mixel combo PHY support for i.MX8qxp phy: freescale: phy-fsl-imx8-mipi-dphy: Add i.MX8qxp LVDS PHY mode support .../bindings/phy/mixel,mipi-dsi-phy.txt | 29 -- .../bindings/phy/mixel,mipi-dsi-phy.yaml | 107 +++++++ drivers/gpu/drm/bridge/nwl-dsi.c | 6 + .../phy/freescale/phy-fsl-imx8-mipi-dphy.c | 276 +++++++++++++++++- include/linux/phy/phy-lvds.h | 32 ++ include/linux/phy/phy.h | 4 + 6 files changed, 414 insertions(+), 40 deletions(-) delete mode 100644 Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt create mode 100644 Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.yaml create mode 100644 include/linux/phy/phy-lvds.h