Message ID | 20220706034810.2352641-1-victor.liu@nxp.com |
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Received: from AM7PR04MB7046.eurprd04.prod.outlook.com (2603:10a6:20b:113::22) by VE1PR04MB6463.eurprd04.prod.outlook.com (2603:10a6:803:11d::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5395.21; Wed, 6 Jul 2022 03:46:33 +0000 Received: from AM7PR04MB7046.eurprd04.prod.outlook.com ([fe80::416e:6e99:bac6:d3a9]) by AM7PR04MB7046.eurprd04.prod.outlook.com ([fe80::416e:6e99:bac6:d3a9%5]) with mapi id 15.20.5395.021; Wed, 6 Jul 2022 03:46:33 +0000 From: Liu Ying <victor.liu@nxp.com> To: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: kishon@ti.com, vkoul@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, krzysztof.kozlowski@linaro.org Subject: [PATCH v4 0/3] phy: freescale: Add i.MX8qm Mixel LVDS PHY support Date: Wed, 6 Jul 2022 11:48:07 +0800 Message-Id: <20220706034810.2352641-1-victor.liu@nxp.com> X-Mailer: git-send-email 2.25.1 X-ClientProxiedBy: SG2P153CA0045.APCP153.PROD.OUTLOOK.COM (2603:1096:4:c6::14) To AM7PR04MB7046.eurprd04.prod.outlook.com (2603:10a6:20b:113::22) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 899736fd-e570-435b-963b-08da5f021eaa X-MS-TrafficTypeDiagnostic: VE1PR04MB6463:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" <linux-phy-bounces@lists.infradead.org> Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org |
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phy: freescale: Add i.MX8qm Mixel LVDS PHY support
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On 06-07-22, 11:48, Liu Ying wrote: > Hi, > > This series aims to add Freescale i.MX8qm LVDS PHY driver and dt-binding > support. > > The PHY IP is from Mixel, Inc. > The PHY IP supports two LVDS PHYs, thus two LVDS channels. > > Each LVDS PHY may work by itself to support a LVDS display device. > > When two LVDS PHYs are enabled simultaneously, PHY configurations and reference > clock rate have to be the same since there is only one set of PHY registers. > In this case, the two LVDS PHYs are usually used to support a dual LVDS link > display device, one as master PHY and the other as slave PHY. Applied, thanks