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b=EyBE6mKCN8MeSepbSpAUYFYYaQh0Y6lXugUDs5cKt6XXdJEvz/zQj1gMwtDHnCizTE42eqYJRDGkRtJx1xTiYfLM/eeMJMyVDGG7IcCVGW/8Vawc1xprMDVvIP5wB7JaldMYCBZmb4uuGj5owOVJhbsWeLUUUhuqFsGNl8r8+2A= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from AM7PR04MB7046.eurprd04.prod.outlook.com (2603:10a6:20b:113::22) by VE1PR04MB6463.eurprd04.prod.outlook.com (2603:10a6:803:11d::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5395.21; Wed, 6 Jul 2022 03:46:33 +0000 Received: from AM7PR04MB7046.eurprd04.prod.outlook.com ([fe80::416e:6e99:bac6:d3a9]) by AM7PR04MB7046.eurprd04.prod.outlook.com ([fe80::416e:6e99:bac6:d3a9%5]) with mapi id 15.20.5395.021; Wed, 6 Jul 2022 03:46:33 +0000 From: Liu Ying To: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: kishon@ti.com, vkoul@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, krzysztof.kozlowski@linaro.org Subject: [PATCH v4 0/3] phy: freescale: Add i.MX8qm Mixel LVDS PHY support Date: Wed, 6 Jul 2022 11:48:07 +0800 Message-Id: <20220706034810.2352641-1-victor.liu@nxp.com> X-Mailer: git-send-email 2.25.1 X-ClientProxiedBy: SG2P153CA0045.APCP153.PROD.OUTLOOK.COM (2603:1096:4:c6::14) To AM7PR04MB7046.eurprd04.prod.outlook.com (2603:10a6:20b:113::22) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 899736fd-e570-435b-963b-08da5f021eaa X-MS-TrafficTypeDiagnostic: VE1PR04MB6463:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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The PHY IP is from Mixel, Inc. The PHY IP supports two LVDS PHYs, thus two LVDS channels. Each LVDS PHY may work by itself to support a LVDS display device. When two LVDS PHYs are enabled simultaneously, PHY configurations and reference clock rate have to be the same since there is only one set of PHY registers. In this case, the two LVDS PHYs are usually used to support a dual LVDS link display device, one as master PHY and the other as slave PHY. Patch 1/3 adds vendor prefix for the PHY IP vendor 'Mixel, Inc.'. Patch 2/3 adds dt-binding for the PHY IP. Patch 3/3 adds PHY driver support. v3->v4: * Use MEGA macro in patch 3/3. (Vinod) * Check slave phy in ->power_off() and power off two phy synchronously in patch 3/3 when necessary. (Vinod) * Use single line for error message in patch 3/3. (Vinod) * Use pm_runtime_resume_and_get() instead of pm_runtime_get_sync() in patch 3/3. (Vinod) v2->v3: * Add Krzysztof's A-b tag on patch 1/3. * Change compatible string from 'mixel,lvds-phy' to 'mixel,28fdsoi-lvds-1250-8ch-tx-pll' in patch 1/3. (Krzysztof) * Rename dt-binding file to 'fsl,imx8qm-lvds-phy.yaml'. (Krzysztof) v1->v2: * Document vendor prefix for the PHY IP vendor 'Mixel, Inc.'. (Krzysztof) * Set fsl,imx8qm-lvds-phy' and 'mixel,lvds-phy' as compatible's enum. (Krzysztof) * Skip 'clock-names' property. (Krzysztof) * Drop 'This patch' from commit messages. (Krzysztof) * Make dev_err_probe() function calls as one-liners. (Krzysztof) * Drop unnecessary debug messages. (Krzysztof) Liu Ying (3): dt-bindings: vendor-prefixes: Add prefix for Mixel, Inc. dt-bindings: phy: Add Freescale i.MX8qm Mixel LVDS PHY binding phy: freescale: Add i.MX8qm Mixel LVDS PHY support .../bindings/phy/fsl,imx8qm-lvds-phy.yaml | 61 +++ .../devicetree/bindings/vendor-prefixes.yaml | 2 + drivers/phy/freescale/Kconfig | 9 + drivers/phy/freescale/Makefile | 1 + .../phy/freescale/phy-fsl-imx8qm-lvds-phy.c | 450 ++++++++++++++++++ 5 files changed, 523 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/fsl,imx8qm-lvds-phy.yaml create mode 100644 drivers/phy/freescale/phy-fsl-imx8qm-lvds-phy.c