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Mon, 31 Oct 2022 11:02:36 -0700 (PDT) Received: from localhost.localdomain ([117.193.209.221]) by smtp.gmail.com with ESMTPSA id q14-20020a170902a3ce00b00186c6d2e7e3sm4742224plb.26.2022.10.31.11.02.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Oct 2022 11:02:34 -0700 (PDT) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: konrad.dybcio@somainline.org, robh+dt@kernel.org, quic_cang@quicinc.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, Manivannan Sadhasivam Subject: [PATCH v2 00/15] ufs: qcom: Add HS-G4 support Date: Mon, 31 Oct 2022 23:32:02 +0530 Message-Id: <20221031180217.32512-1-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221031_110239_651636_3740B4C8 X-CRM114-Status: GOOD ( 14.24 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Hello, This series adds HS-G4 support to the Qcom UFS driver and PHY driver. The newer Qcom platforms support configuring the UFS controller and PHY in dual gears (i.e., controller/PHY can be configured to run in two gear speeds). This is accomplished by adding two different PHY init sequences to the PHY driver and the UFS driver requesting the one that's required based on the platform configuration. But this requires both the UFS controller and UFS device to agree to a common gear. For finding the max supported gear, a separate register is used for the UFS controller and devicetree is used for the UFS device. Based on the max gear of both, the UFS driver will decide which gear to use during runtime. This series has been tested on Qcom RB5 development platform powered by SM8250 SoC that uses HS-G4. Merging Strategy: ----------------- The PHY patches are expected to go through PHY tree and UFS, MAINTAINERS patches are expected to go through SCSI tree. Finally, the binding and devicetree patches can go through ARM MSM tree. There is no build dependency between the patches. Thanks, Mani Changes in v2: * Collected reviews from Dmitry * Renamed "max-gear" property to "max-device-gear" * Used min() for deciding which gear to use instead of open comparision * Added comment about the old register name Manivannan Sadhasivam (15): phy: qcom-qmp-ufs: Move register settings to qmp_phy_cfg_tables struct phy: qcom-qmp-ufs: Add support for configuring PHY in HS Series B mode phy: qcom-qmp-ufs: Add support for configuring PHY in HS G4 mode phy: qcom-qmp-ufs: Add HS G4 mode support to SM8250 SoC phy: qcom-qmp-ufs: Move HS Rate B register setting to tables_hs_b dt-bindings: ufs: Add "max-device-gear" property for UFS device arm64: dts: qcom: qrb5165-rb5: Add max-device-gear property to UFS node scsi: ufs: ufs-qcom: Remove un-necessary goto statements scsi: ufs: ufs-qcom: Remove un-necessary WARN_ON() scsi: ufs: ufs-qcom: Use bitfields where appropriate scsi: ufs: ufs-qcom: Use dev_err_probe() for printing probe error scsi: ufs: ufs-qcom: Fix the Qcom register name for offset 0xD0 scsi: ufs: ufs-qcom: Factor out the logic finding the HS Gear scsi: ufs: ufs-qcom: Add support for finding HS gear on new UFS versions MAINTAINERS: Add myself as the maintainer for Qcom UFS driver .../devicetree/bindings/ufs/ufs-common.yaml | 5 + MAINTAINERS | 8 + arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 1 + drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 350 +++++++++++++----- drivers/ufs/host/ufs-qcom.c | 175 +++++---- drivers/ufs/host/ufs-qcom.h | 68 ++-- 6 files changed, 390 insertions(+), 217 deletions(-)