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Thu, 19 Jan 2023 06:05:06 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id m10-20020a05600c4f4a00b003d96efd09b7sm5263883wmq.19.2023.01.19.06.05.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Jan 2023 06:05:05 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Krzysztof Kozlowski , Lorenzo Pieralisi , "vkoul@kernel.org" , Kishon Vijay Abraham I , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, Linux Kernel Mailing List Subject: [PATCH v4 00/12] sm8550: Add PCIe HC and PHY support Date: Thu, 19 Jan 2023 16:04:41 +0200 Message-Id: <20230119140453.3942340-1-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230119_060509_944130_C0978C81 X-CRM114-Status: GOOD ( 10.08 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org In order to make sure the bindings are properly updated, I decided to send the whole PCIe support for SM8550 in a single patchset. Sorry in advance for the inconvenience. For changelogs please look at each patch individually. Abel Vesa (12): dt-bindings: phy: Add QMP PCIe PHY comptible for SM8550 phy: qcom-qmp: pcs: Add v6 register offsets phy: qcom-qmp: pcs: Add v6.20 register offsets phy: qcom-qmp: pcs-pcie: Add v6 register offsets phy: qcom-qmp: pcs-pcie: Add v6.20 register offsets phy: qcom-qmp: qserdes-txrx: Add v6.20 register offsets phy: qcom-qmp: qserdes-lane-shared: Add v6 register offsets phy: qcom-qmp-pcie: Add support for SM8550 g3x2 and g4x2 PCIEs dt-bindings: PCI: qcom: Add SM8550 compatible PCI: qcom: Add SM8550 PCIe support arm64: dts: qcom: sm8550: Add PCIe PHYs and controllers nodes arm64: dts: qcom: sm8550-mtp: Add PCIe PHYs and controllers nodes .../devicetree/bindings/pci/qcom,pcie.yaml | 44 +++ .../phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 11 +- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 29 ++ arch/arm64/boot/dts/qcom/sm8550.dtsi | 207 +++++++++- drivers/pci/controller/dwc/pcie-qcom.c | 4 +- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 367 ++++++++++++++++++ .../phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h | 15 + .../qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h | 23 ++ drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6.h | 16 + drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h | 18 + .../phy-qcom-qmp-qserdes-ln-shrd-v6.h | 32 ++ .../phy-qcom-qmp-qserdes-txrx-v6_20.h | 45 +++ drivers/phy/qualcomm/phy-qcom-qmp.h | 6 + 13 files changed, 812 insertions(+), 5 deletions(-) create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6.h create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-ln-shrd-v6.h create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h