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Mon, 23 Sep 2024 12:57:15 +0000 Received: from NALASPPMTA01.qualcomm.com (NALASPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 48NCspIr030063; Mon, 23 Sep 2024 12:57:15 GMT Received: from hu-devc-lv-u22-c.qualcomm.com (hu-qianyu-lv.qualcomm.com [10.81.25.114]) by NALASPPMTA01.qualcomm.com (PPS) with ESMTPS id 48NCvFZK001738 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 23 Sep 2024 12:57:15 +0000 Received: by hu-devc-lv-u22-c.qualcomm.com (Postfix, from userid 4098150) id 33E6265F; Mon, 23 Sep 2024 05:57:15 -0700 (PDT) From: Qiang Yu To: manivannan.sadhasivam@linaro.org, vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, andersson@kernel.org, konradybcio@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, abel.vesa@linaro.org, quic_msarkar@quicinc.com, quic_devipriy@quicinc.com Cc: dmitry.baryshkov@linaro.org, kw@linux.com, lpieralisi@kernel.org, neil.armstrong@linaro.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Qiang Yu Subject: [PATCH v3 0/6] Add support for PCIe3 on x1e80100 Date: Mon, 23 Sep 2024 05:57:07 -0700 Message-Id: <20240923125713.3411487-1-quic_qianyu@quicinc.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: lF6GgPoAvUms48r_roaOuiMcm6VsPBEQ X-Proofpoint-GUID: lF6GgPoAvUms48r_roaOuiMcm6VsPBEQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxlogscore=888 spamscore=0 lowpriorityscore=0 adultscore=0 mlxscore=0 suspectscore=0 malwarescore=0 phishscore=0 impostorscore=0 clxscore=1015 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409230095 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240923_055734_425977_7D85B87B X-CRM114-Status: GOOD ( 14.24 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org This series add support for PCIe3 on x1e80100. PCIe3 needs additional set of clocks, regulators and new set of PCIe QMP PHY configuration compare other PCIe instances on x1e80100. Hence add required resource configuration and usage for PCIe3. v2->v3: 1. Use 'Gen 4 x8' in commit msg 2. Move opp-table property to qcom,pcie-common.yaml 3. Add Reviewed-by tag 4. Add global interrupt and use GIC_SPI for the parent interrupt specifier 5. Use 0x0 in reg property and use pcie@ for pcie3 device node 6. Show different IP version v6.30 in commit msg 7. Add logic in controller driver to have new ops for x1e80100 v2->v1: 1. Squash [PATCH 1/8], [PATCH 2/8],[PATCH 3/8] into one patch and make the indentation consistent. 2. Put dts patch at the end of the patchset. 3. Put dt-binding patch at the first of the patchset. 4. Add a new patch where opp-table is added in dt-binding to avoid dtbs checking error. 5. Remove GCC_PCIE_3_AUX_CLK, RPMH_CXO_CLK, put in TCSR_PCIE_8L_CLKREF_EN as ref. 6. Remove lane_broadcasting. 7. Add 64 bit bar, Remove GCC_PCIE_3_PIPE_CLK_SRC, GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK is changed to GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK. 8. Add Reviewed-by tag. 9. Remove [PATCH 7/8], [PATCH 8/8]. Qiang Yu (6): dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 QMP PCIe PHY Gen4 x8 dt-bindings: PCI: qcom: Add OPP table for X1E80100 phy: qcom: qmp: Add phy register and clk setting for x1e80100 PCIe3 clk: qcom: gcc-x1e80100: Fix halt_check for pipediv2 clocks PCI: qcom: Add new cfg and ops without config_sid callback for X1E80100 arm64: dts: qcom: x1e80100: Add support for PCIe3 on x1e80100 .../bindings/pci/qcom,pcie-common.yaml | 4 + .../phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 3 + arch/arm64/boot/dts/qcom/x1e80100.dtsi | 204 ++++++++++++++++- drivers/clk/qcom/gcc-x1e80100.c | 10 +- drivers/pci/controller/dwc/pcie-qcom.c | 16 +- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 211 ++++++++++++++++++ .../qualcomm/phy-qcom-qmp-pcs-pcie-v6_30.h | 25 +++ drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_30.h | 19 ++ 8 files changed, 485 insertions(+), 7 deletions(-) create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_30.h create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_30.h