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Tue, 21 Jan 2025 09:42:45 +0000 Received: from APTAIPPMTA02.qualcomm.com (APTAIPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 50L9gjC3003206; Tue, 21 Jan 2025 09:42:45 GMT Received: from cbsp-sh-gv.ap.qualcomm.com (CBSP-SH-gv.ap.qualcomm.com [10.231.249.68]) by APTAIPPMTA02.qualcomm.com (PPS) with ESMTPS id 50L9gikk003204 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 21 Jan 2025 09:42:45 +0000 Received: by cbsp-sh-gv.ap.qualcomm.com (Postfix, from userid 4635958) id 9DCD740BBC; Tue, 21 Jan 2025 17:42:43 +0800 (CST) From: Wenbin Yao To: vkoul@kernel.org, kishon@kernel.org, p.zabel@pengutronix.de, dmitry.baryshkov@linaro.org, abel.vesa@linaro.org, quic_qianyu@quicinc.com, neil.armstrong@linaro.org, manivannan.sadhasivam@linaro.org, quic_devipriy@quicinc.com, konrad.dybcio@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org Cc: quic_wenbyao@quicinc.com Subject: [PATCH 0/2] phy: qcom: qmp-pcie: Add PCIe PHY no_csr reset support Date: Tue, 21 Jan 2025 17:41:38 +0800 Message-Id: <20250121094140.4006801-1-quic_wenbyao@quicinc.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: va46TrQU8P5630v08xyn9jcs9A4atPxE X-Proofpoint-GUID: va46TrQU8P5630v08xyn9jcs9A4atPxE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-21_05,2025-01-21_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 clxscore=1011 adultscore=0 mlxscore=0 impostorscore=0 mlxlogscore=874 malwarescore=0 bulkscore=0 suspectscore=0 phishscore=0 lowpriorityscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501210079 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250121_014252_418728_5D7158F6 X-CRM114-Status: UNSURE ( 7.59 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org The series aims to skip phy register programming and drive PCIe PHY with register setting programmed in bootloader by simply toggling no_csr reset, which once togglled, PHY hardware will be reset while PHY registers are retained. First, determine whether PHY setting can be skipped by checking QPHY_START_CTRL register and the existence of nocsr reset. If it is programmed and no_csr reset is supported, do no_csr reset and skip BCR reset which will reset entire PHY. This series also remove has_nocsr_reset flag in qmp_phy_cfg structure and decide whether the PHY supports nocsr reset by checking the existence of nocsr reset in device tree. The series are tested on X1E80100-QCP and HDK8550. Wenbin Yao (2): phy: qcom: pcie: Determine has_nocsr_reset dynamically phy: qcom: qmp-pcie: Add PHY register retention support drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 109 ++++++++++++++--------- 1 file changed, 65 insertions(+), 44 deletions(-) base-commit: bcf2acd8f64b0a5783deeeb5fd70c6163ec5acd7