From patchwork Fri Jul 23 08:22:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Q2h1bmZlbmcgWXVuICjkupHmmKXls7Ap?= X-Patchwork-Id: 12395555 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2F66FC4338F for ; Fri, 23 Jul 2021 08:32:08 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EAE2E60E77 for ; Fri, 23 Jul 2021 08:32:07 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org EAE2E60E77 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=29lJp7gcFDPXKiFnA7HRjkBKUZ09eFascaSeOdIzNLQ=; b=KYns6LwS/qecXD qBJ+3q3LQk1a3UActpb7PixLgrbf1dndgEI/LfLuBBPnh1wtD1FJBU0Zy0YRPBNgtK2YXPB3lgSkz d4o/4W9PrRFbNd41KNs4RBtJb/oWoQB383dX/qLxKL6qmYiBRPalhkPsv30NsIzcrkTOJLLuTm7Df OGhXsl2Vn6eGNp7jAdsolZuJOotFnoV4oY/eZ4SKt4FAP25yB/NZwRSnfxQ72Mr5x4sA9roqvyCIA oKmkmFX//puAF4gNLVUTTIiejMOvmSGnHQEUnMWkiPBbwI9VZye5woPlstfR2q9lNUNwdhCCf2Wzs 2GAWpQ+Mee6frytNpEiQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1m6qbH-003wh2-Eb; Fri, 23 Jul 2021 08:32:07 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1m6qam-003wTe-Jz; Fri, 23 Jul 2021 08:31:38 +0000 X-UUID: bce383a2be3346b5b5d91e1c0f60de64-20210723 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=YKE8ZkD3iBELPfGaAubKLuSv851dIScDkR+xfgn+YjE=; b=HTn55g01Ng0n7xcBaq5Sh63rl3had8dxP/unt2bI2CK3Q+VhMsHa7H4agJ4LzEQLvP+d8H3HeDhACSSL6pE41ik+ORrmm+YD8/n8OADvGed+7gDZah4FWyOV+qA23bJqLIxf8DoAu/Mn5cm9WkGtJMUkK0wSsDe68yYhLy92FNQ=; X-UUID: bce383a2be3346b5b5d91e1c0f60de64-20210723 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 570865691; Fri, 23 Jul 2021 01:31:32 -0700 Received: from MTKMBS06N1.mediatek.inc (172.21.101.129) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 23 Jul 2021 01:23:19 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs06n1.mediatek.inc (172.21.101.129) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 23 Jul 2021 16:23:18 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 23 Jul 2021 16:23:17 +0800 From: Chunfeng Yun To: Vinod Koul CC: Chunfeng Yun , Kishon Vijay Abraham I , Rob Herring , Matthias Brugger , , , , , , Eddie Hung Subject: [PATCH v4 1/3] dt-bindings: phy: mediatek: tphy: add support hardware version 3 Date: Fri, 23 Jul 2021 16:22:40 +0800 Message-ID: <1627028562-23584-1-git-send-email-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210723_013136_705524_49733328 X-CRM114-Status: GOOD ( 14.11 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org The PHYA architecture is updated, and doesn't support slew rate calibration anymore on 7nm or advanced process, add a new version number to support it. Due to the FreqMeter bank is not used but reserved, it's backward with v2 until now. For mt8195, no function changes when use generic v2 or v3 compatible, but prefer to use v3's compatible, it will not waste the time to calibrate the slew rate, and also correspond with hardware version. Acked-by: Rob Herring Signed-off-by: Chunfeng Yun --- v4: no changes v3: add Acked-by Rob v2: add more commit log suggested by Rob --- .../devicetree/bindings/phy/mediatek,tphy.yaml | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml index ef9d9d4e6875..838852cb8527 100644 --- a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml +++ b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml @@ -15,7 +15,7 @@ description: | controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA. Layout differences of banks between T-PHY V1 (mt8173/mt2701) and - T-PHY V2 (mt2712) when works on USB mode: + T-PHY V2 (mt2712) / V3 (mt8195) when works on USB mode: ----------------------------------- Version 1: port offset bank @@ -34,7 +34,7 @@ description: | u2 port2 0x1800 U2PHY_COM ... - Version 2: + Version 2/3: port offset bank u2 port0 0x0000 MISC 0x0100 FMREG @@ -59,7 +59,8 @@ description: | SPLLC shared by u3 ports and FMREG shared by u2 ports on V1 are put back into each port; a new bank MISC for u2 ports and CHIP for u3 ports are - added on V2. + added on V2; the FMREG bank for slew rate calibration is not used anymore + and reserved on V3; properties: $nodename: @@ -79,8 +80,11 @@ properties: - mediatek,mt2712-tphy - mediatek,mt7629-tphy - mediatek,mt8183-tphy - - mediatek,mt8195-tphy - const: mediatek,generic-tphy-v2 + - items: + - enum: + - mediatek,mt8195-tphy + - const: mediatek,generic-tphy-v3 - const: mediatek,mt2701-u3phy deprecated: true - const: mediatek,mt2712-u3phy @@ -91,7 +95,7 @@ properties: description: Register shared by multiple ports, exclude port's private register. It is needed for T-PHY V1, such as mt2701 and mt8173, but not for - T-PHY V2, such as mt2712. + T-PHY V2/V3, such as mt2712. maxItems: 1 "#address-cells":