@@ -289,6 +289,10 @@ pca6416: gpio@20 {
};
};
+&pcie_phy {
+ status = "okay";
+};
+
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
@@ -998,6 +998,18 @@ usbmisc2: usbmisc@32e50200 {
reg = <0x32e50200 0x200>;
};
+ pcie_phy: pcie-phy@32f00000 {
+ compatible = "fsl,imx8mm-pcie-phy";
+ reg = <0x32f00000 0x10000>;
+ clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
+ clock-names = "phy";
+ assigned-clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
+ assigned-clock-rates = <100000000>;
+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_100M>;
+ #phy-cells = <0>;
+ fsl,refclk-pad-mode = <1>;
+ status = "disabled";
+ };
};
dma_apbh: dma-controller@33000000 {
Add the PCIe PHY support on iMX8MM platforms. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> --- arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 4 ++++ arch/arm64/boot/dts/freescale/imx8mm.dtsi | 12 ++++++++++++ 2 files changed, 16 insertions(+)