| Message ID | 1632641983-1455-4-git-send-email-hongxing.zhu@nxp.com |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | add the imx8 pcie phy driver support | expand |
Am Sonntag, dem 26.09.2021 um 15:39 +0800 schrieb Richard Zhu: > Add the PCIe PHY support on iMX8MM platforms. > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> > --- > arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 4 ++++ > arch/arm64/boot/dts/freescale/imx8mm.dtsi | 12 ++++++++++++ This should be split into 2 patches: one for the SoC and one for the EVK board. > 2 files changed, 16 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi > index e033d0257b5a..e7f398433486 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi > @@ -289,6 +289,10 @@ pca6416: gpio@20 { > }; > }; > > +&pcie_phy { > + status = "okay"; > +}; > + > &sai3 { > pinctrl-names = "default"; > pinctrl-0 = <&pinctrl_sai3>; > diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > index e7648c3b8390..de231d531ba4 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > @@ -998,6 +998,18 @@ usbmisc2: usbmisc@32e50200 { > reg = <0x32e50200 0x200>; > }; > > + pcie_phy: pcie-phy@32f00000 { > + compatible = "fsl,imx8mm-pcie-phy"; > + reg = <0x32f00000 0x10000>; > + clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; > + clock-names = "phy"; > + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; > + assigned-clock-rates = <100000000>; > + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_100M>; > + #phy-cells = <0>; > + fsl,refclk-pad-mode = <1>; Move this to the board DT, as the pad mode is a board level decision. Also use the enum instead of raw value. > + status = "disabled"; > + }; > }; > > dma_apbh: dma-controller@33000000 {
> -----Original Message----- > From: Lucas Stach <l.stach@pengutronix.de> > Sent: Monday, September 27, 2021 4:35 PM > To: Richard Zhu <hongxing.zhu@nxp.com>; kishon@ti.com; vkoul@kernel.org; > robh@kernel.org; galak@kernel.crashing.org; shawnguo@kernel.org > Cc: linux-phy@lists.infradead.org; devicetree@vger.kernel.org; > linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org; > kernel@pengutronix.de; dl-linux-imx <linux-imx@nxp.com> > Subject: Re: [PATCH v2 3/4] arm64: dts: imx8mm: add the pcie phy support > > Am Sonntag, dem 26.09.2021 um 15:39 +0800 schrieb Richard Zhu: > > Add the PCIe PHY support on iMX8MM platforms. > > > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> > > --- > > arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 4 ++++ > > arch/arm64/boot/dts/freescale/imx8mm.dtsi | 12 ++++++++++++ > > This should be split into 2 patches: one for the SoC and one for the EVK board. > [Richard Zhu] Okay, would split this patch into 2 patches later. Thanks. > > 2 files changed, 16 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi > > b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi > > index e033d0257b5a..e7f398433486 100644 > > --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi > > +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi > > @@ -289,6 +289,10 @@ pca6416: gpio@20 { > > }; > > }; > > > > +&pcie_phy { > > + status = "okay"; > > +}; > > + > > &sai3 { > > pinctrl-names = "default"; > > pinctrl-0 = <&pinctrl_sai3>; > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi > > b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > > index e7648c3b8390..de231d531ba4 100644 > > --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi > > +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > > @@ -998,6 +998,18 @@ usbmisc2: usbmisc@32e50200 { > > reg = <0x32e50200 0x200>; > > }; > > > > + pcie_phy: pcie-phy@32f00000 { > > + compatible = "fsl,imx8mm-pcie-phy"; > > + reg = <0x32f00000 0x10000>; > > + clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; > > + clock-names = "phy"; > > + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; > > + assigned-clock-rates = <100000000>; > > + assigned-clock-parents = <&clk > IMX8MM_SYS_PLL2_100M>; > > + #phy-cells = <0>; > > + fsl,refclk-pad-mode = <1>; > > Move this to the board DT, as the pad mode is a board level decision. > Also use the enum instead of raw value. [Richard Zhu] Got that, thanks. > > > + status = "disabled"; > > + }; > > }; > > > > dma_apbh: dma-controller@33000000 { >
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi index e033d0257b5a..e7f398433486 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi @@ -289,6 +289,10 @@ pca6416: gpio@20 { }; }; +&pcie_phy { + status = "okay"; +}; + &sai3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai3>; diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index e7648c3b8390..de231d531ba4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -998,6 +998,18 @@ usbmisc2: usbmisc@32e50200 { reg = <0x32e50200 0x200>; }; + pcie_phy: pcie-phy@32f00000 { + compatible = "fsl,imx8mm-pcie-phy"; + reg = <0x32f00000 0x10000>; + clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; + clock-names = "phy"; + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; + assigned-clock-rates = <100000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_100M>; + #phy-cells = <0>; + fsl,refclk-pad-mode = <1>; + status = "disabled"; + }; }; dma_apbh: dma-controller@33000000 {
Add the PCIe PHY support on iMX8MM platforms. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> --- arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 4 ++++ arch/arm64/boot/dts/freescale/imx8mm.dtsi | 12 ++++++++++++ 2 files changed, 16 insertions(+)