From patchwork Thu May 9 05:56:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Zhu X-Patchwork-Id: 13659474 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 96C8AC10F1A for ; Thu, 9 May 2024 06:15:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=SlXKbxg1i0h6OmUXBvm7RT7xtp8ETQqUX2arOIruUe4=; b=iGcVdSxPz+kqEU mXVTYtA/LfAfjNQwjTq+2SPE8aC7vfKs1FWhaE2JTKPoKF5wrqH+JfL6dbwW1cgOOd6VnLWaotC8w fhhthGu6ns3u86L9YWLpn6a74PC6JFMSQqiDbLp3x8MY6R0rebuAmMz4jbQCzLhsf5JLPbuxGPZ6p p+32fKm2F2B/c1qQF3olJx6sIGemoHa0tIlIskpNz5LdoBAvdXaXBd6SiQx24Jw4aByvU/QfvUGhI ud7SozHs4Z1AjCI9dcwbL0j6Mto8cXw+slSH9s0Bklt7hm9Oeac6fgYjJV92Yuin9IjlNgVEMXuvg PMi7Gg0oatvMakP/sOIw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1s4x4G-00000000Xmo-0dM4; Thu, 09 May 2024 06:15:48 +0000 Received: from inva020.nxp.com ([92.121.34.13]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1s4x4A-00000000XjO-2Mmc; Thu, 09 May 2024 06:15:43 +0000 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 52E981A1F47; Thu, 9 May 2024 08:15:41 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 090291A1F45; Thu, 9 May 2024 08:15:41 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 111D4183486A; Thu, 9 May 2024 14:15:39 +0800 (+08) From: Richard Zhu To: conor@kernel.org, vkoul@kernel.org, kishon@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, frank.li@nxp.com, conor+dt@kernel.org Cc: hongxing.zhu@nxp.com, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, imx@lists.linux.dev Subject: [PATCH v4 1/3] dt-bindings: phy: phy-imx8-pcie: Add header file for i.MX8Q HSIO SerDes PHY Date: Thu, 9 May 2024 13:56:19 +0800 Message-Id: <1715234181-672-2-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1715234181-672-1-git-send-email-hongxing.zhu@nxp.com> References: <1715234181-672-1-git-send-email-hongxing.zhu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240508_231542_764895_A8B77707 X-CRM114-Status: UNSURE ( 9.40 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Add lane index and HSIO configuration definitions of the i.MX8Q HSIO SerDes PHY into header file. Signed-off-by: Richard Zhu Reviewed-by: Frank Li --- include/dt-bindings/phy/phy-imx8-pcie.h | 29 +++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/include/dt-bindings/phy/phy-imx8-pcie.h b/include/dt-bindings/phy/phy-imx8-pcie.h index 8bbe2d6538d8..8f65a77fca09 100644 --- a/include/dt-bindings/phy/phy-imx8-pcie.h +++ b/include/dt-bindings/phy/phy-imx8-pcie.h @@ -11,4 +11,33 @@ #define IMX8_PCIE_REFCLK_PAD_INPUT 1 #define IMX8_PCIE_REFCLK_PAD_OUTPUT 2 +/* + * Regarding the design of i.MX8QM HSIO subsystem, HSIO module can be + * confiured as following three use cases. + * + * Define different configurations refer to the use cases, since it is + * mandatory required in the initialization. + * + * On i.MX8QXP, HSIO module only has PCIEB and one lane PHY. + * Define "IMX8Q_HSIO_CFG_PCIEB" for i.MX8QXP platforms. + * + * +----------------------------------------------------+----------+ + * | | i.MX8QM | i.MX8QXP | + * |-------------------------------|--------------------|----------| + * | | Lane0| Lane1| Lane2| Lane0 | + * |-------------------------------|------|------|------|----------| + * | IMX8Q_HSIO_CFG_PCIEAX2SATA | PCIEA| PCIEA| SATA | | + * |-------------------------------|------|------|------|----------| + * | IMX8Q_HSIO_CFG_PCIEAX2PCIEB | PCIEA| PCIEA| PCIEB| | + * |-------------------------------|------|------|------|----------| + * | IMX8Q_HSIO_CFG_PCIEAPCIEBSATA | PCIEA| PCIEB| SATA | | + * |-------------------------------|------|------|------|----------| + * | IMX8Q_HSIO_CFG_PCIEB | - | - | - | PCIEB | + * +----------------------------------------------------+----------+ + */ +#define IMX8Q_HSIO_CFG_PCIEAX2SATA 0x1 +#define IMX8Q_HSIO_CFG_PCIEAX2PCIEB 0x2 +#define IMX8Q_HSIO_CFG_PCIEAPCIEBSATA (IMX8Q_HSIO_CFG_PCIEAX2SATA | IMX8Q_HSIO_CFG_PCIEAX2PCIEB) +#define IMX8Q_HSIO_CFG_PCIEB IMX8Q_HSIO_CFG_PCIEAX2PCIEB + #endif /* _DT_BINDINGS_IMX8_PCIE_H */