| Message ID | 20210706020625.117400-3-chanho61.park@samsung.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Support exynosautov9 ufs phy driver | expand |
On 7/6/21 11:06 AM, Chanho Park wrote: > This patch adds to support phy-exynosautov9-ufs driver for ExynosAuto v9 > series SoCs. The patch adds "samsung,exynosautov9-ufs-phy" compatible. > Unlike previous exynos ufs phy, the chip uses 0x50 offset as > PHY_TRSV_REG_CFG_OFFSET. > > Change-Id: I4ea333d4565af537c26a8876d1b27144eea3c3c6 Remove Change-Id. Best Regards, Jaehoon Chung > Signed-off-by: Chanho Park <chanho61.park@samsung.com> > --- > .../bindings/phy/samsung,ufs-phy.yaml | 1 + > drivers/phy/samsung/Makefile | 3 +- > drivers/phy/samsung/phy-exynosautov9-ufs.c | 70 +++++++++++++++++++ > drivers/phy/samsung/phy-samsung-ufs.c | 3 + > drivers/phy/samsung/phy-samsung-ufs.h | 8 ++- > 5 files changed, 82 insertions(+), 3 deletions(-) > create mode 100644 drivers/phy/samsung/phy-exynosautov9-ufs.c > > diff --git a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml > index 636cc501b54f..f6ed1a005e7a 100644 > --- a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml > +++ b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml > @@ -16,6 +16,7 @@ properties: > compatible: > enum: > - samsung,exynos7-ufs-phy > + - samsung,exynosautov9-ufs-phy > > reg: > maxItems: 1 > diff --git a/drivers/phy/samsung/Makefile b/drivers/phy/samsung/Makefile > index d55d9aa5b932..ab87b71cd90f 100644 > --- a/drivers/phy/samsung/Makefile > +++ b/drivers/phy/samsung/Makefile > @@ -3,7 +3,8 @@ obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o > obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o > obj-$(CONFIG_PHY_EXYNOS_PCIE) += phy-exynos-pcie.o > obj-$(CONFIG_PHY_SAMSUNG_UFS) += phy-samsung-ufs.o \ > - phy-exynos7-ufs.o > + phy-exynos7-ufs.o \ > + phy-exynosautov9-ufs.o > obj-$(CONFIG_PHY_SAMSUNG_USB2) += phy-exynos-usb2.o > phy-exynos-usb2-y += phy-samsung-usb2.o > phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4210_USB2) += phy-exynos4210-usb2.o > diff --git a/drivers/phy/samsung/phy-exynosautov9-ufs.c b/drivers/phy/samsung/phy-exynosautov9-ufs.c > new file mode 100644 > index 000000000000..9ab79e018724 > --- /dev/null > +++ b/drivers/phy/samsung/phy-exynosautov9-ufs.c > @@ -0,0 +1,70 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * UFS PHY driver data for Samsung EXYNOSAUTO v9 SoC > + * > + * Copyright (C) 2021 Samsung Electronics Co., Ltd. > + */ > + > +#include <linux/io.h> > +#include <linux/phy/phy.h> > + > +#include "phy-samsung-ufs.h" > + > +#define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL 0x728 > +#define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1 > +#define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0) > + > +#define PHY_TRSV_REG_CFG_AUTOV9(o, v, d) \ > + PHY_TRSV_REG_CFG_OFFSET(o, v, d, 0x50) > + > +/* Calibration for phy initialization */ > +static const struct samsung_ufs_phy_cfg exynosautov9_pre_init_cfg[] = { > + PHY_COMN_REG_CFG(0x023, 0x80, PWR_MODE_ANY), > + PHY_COMN_REG_CFG(0x01d, 0x10, PWR_MODE_ANY), > + > + PHY_TRSV_REG_CFG_AUTOV9(0x044, 0xb5, PWR_MODE_ANY), > + PHY_TRSV_REG_CFG_AUTOV9(0x04d, 0x43, PWR_MODE_ANY), > + PHY_TRSV_REG_CFG_AUTOV9(0x05b, 0x20, PWR_MODE_ANY), > + PHY_TRSV_REG_CFG_AUTOV9(0x05e, 0xc0, PWR_MODE_ANY), > + PHY_TRSV_REG_CFG_AUTOV9(0x038, 0x12, PWR_MODE_ANY), > + PHY_TRSV_REG_CFG_AUTOV9(0x059, 0x58, PWR_MODE_ANY), > + PHY_TRSV_REG_CFG_AUTOV9(0x06c, 0x18, PWR_MODE_ANY), > + PHY_TRSV_REG_CFG_AUTOV9(0x06d, 0x02, PWR_MODE_ANY), > + > + PHY_COMN_REG_CFG(0x023, 0xc0, PWR_MODE_ANY), > + PHY_COMN_REG_CFG(0x023, 0x00, PWR_MODE_ANY), > + > + PHY_TRSV_REG_CFG(0x042, 0x5d, PWR_MODE_ANY), > + PHY_TRSV_REG_CFG(0x043, 0x80, PWR_MODE_ANY), > + > + END_UFS_PHY_CFG, > +}; > + > +/* Calibration for HS mode series A/B */ > +static const struct samsung_ufs_phy_cfg exynosautov9_pre_pwr_hs_cfg[] = { > + PHY_TRSV_REG_CFG(0x032, 0xbc, PWR_MODE_HS_ANY), > + PHY_TRSV_REG_CFG(0x03c, 0x7f, PWR_MODE_HS_ANY), > + PHY_TRSV_REG_CFG(0x048, 0xc0, PWR_MODE_HS_ANY), > + > + PHY_TRSV_REG_CFG(0x04a, 0x00, PWR_MODE_HS_G3_SER_B), > + PHY_TRSV_REG_CFG(0x04b, 0x10, PWR_MODE_HS_G1_SER_B | > + PWR_MODE_HS_G3_SER_B), > + PHY_TRSV_REG_CFG(0x04d, 0x63, PWR_MODE_HS_G3_SER_B), > + > + END_UFS_PHY_CFG, > +}; > + > +static const struct samsung_ufs_phy_cfg *exynosautov9_ufs_phy_cfgs[CFG_TAG_MAX] = { > + [CFG_PRE_INIT] = exynosautov9_pre_init_cfg, > + [CFG_PRE_PWR_HS] = exynosautov9_pre_pwr_hs_cfg, > +}; > + > +const struct samsung_ufs_phy_drvdata exynosautov9_ufs_phy = { > + .cfg = exynosautov9_ufs_phy_cfgs, > + .isol = { > + .offset = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL, > + .mask = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_MASK, > + .en = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_EN, > + }, > + .has_symbol_clk = 0, > +}; > diff --git a/drivers/phy/samsung/phy-samsung-ufs.c b/drivers/phy/samsung/phy-samsung-ufs.c > index dd9ab1519d83..602ddef259eb 100644 > --- a/drivers/phy/samsung/phy-samsung-ufs.c > +++ b/drivers/phy/samsung/phy-samsung-ufs.c > @@ -347,6 +347,9 @@ static const struct of_device_id samsung_ufs_phy_match[] = { > { > .compatible = "samsung,exynos7-ufs-phy", > .data = &exynos7_ufs_phy, > + }, { > + .compatible = "samsung,exynosautov9-ufs-phy", > + .data = &exynosautov9_ufs_phy, > }, > {}, > }; > diff --git a/drivers/phy/samsung/phy-samsung-ufs.h b/drivers/phy/samsung/phy-samsung-ufs.h > index 1532d239ff0e..b9b85d55a2d5 100644 > --- a/drivers/phy/samsung/phy-samsung-ufs.h > +++ b/drivers/phy/samsung/phy-samsung-ufs.h > @@ -26,14 +26,17 @@ > .id = PHY_COMN_BLK, \ > } > > -#define PHY_TRSV_REG_CFG(o, v, d) { \ > +#define PHY_TRSV_REG_CFG_OFFSET(o, v, d, c) { \ > .off_0 = PHY_APB_ADDR((o)), \ > - .off_1 = PHY_APB_ADDR((o) + PHY_TRSV_CH_OFFSET), \ > + .off_1 = PHY_APB_ADDR((o) + (c)), \ > .val = (v), \ > .desc = (d), \ > .id = PHY_TRSV_BLK, \ > } > > +#define PHY_TRSV_REG_CFG(o, v, d) \ > + PHY_TRSV_REG_CFG_OFFSET(o, v, d, PHY_TRSV_CH_OFFSET) > + > /* UFS PHY registers */ > #define PHY_PLL_LOCK_STATUS 0x1e > #define PHY_CDR_LOCK_STATUS 0x5e > @@ -137,5 +140,6 @@ static inline void samsung_ufs_phy_ctrl_isol( > } > > extern const struct samsung_ufs_phy_drvdata exynos7_ufs_phy; > +extern const struct samsung_ufs_phy_drvdata exynosautov9_ufs_phy; > > #endif /* _PHY_SAMSUNG_UFS_ */ >
diff --git a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml index 636cc501b54f..f6ed1a005e7a 100644 --- a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml +++ b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml @@ -16,6 +16,7 @@ properties: compatible: enum: - samsung,exynos7-ufs-phy + - samsung,exynosautov9-ufs-phy reg: maxItems: 1 diff --git a/drivers/phy/samsung/Makefile b/drivers/phy/samsung/Makefile index d55d9aa5b932..ab87b71cd90f 100644 --- a/drivers/phy/samsung/Makefile +++ b/drivers/phy/samsung/Makefile @@ -3,7 +3,8 @@ obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o obj-$(CONFIG_PHY_EXYNOS_PCIE) += phy-exynos-pcie.o obj-$(CONFIG_PHY_SAMSUNG_UFS) += phy-samsung-ufs.o \ - phy-exynos7-ufs.o + phy-exynos7-ufs.o \ + phy-exynosautov9-ufs.o obj-$(CONFIG_PHY_SAMSUNG_USB2) += phy-exynos-usb2.o phy-exynos-usb2-y += phy-samsung-usb2.o phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4210_USB2) += phy-exynos4210-usb2.o diff --git a/drivers/phy/samsung/phy-exynosautov9-ufs.c b/drivers/phy/samsung/phy-exynosautov9-ufs.c new file mode 100644 index 000000000000..9ab79e018724 --- /dev/null +++ b/drivers/phy/samsung/phy-exynosautov9-ufs.c @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * UFS PHY driver data for Samsung EXYNOSAUTO v9 SoC + * + * Copyright (C) 2021 Samsung Electronics Co., Ltd. + */ + +#include <linux/io.h> +#include <linux/phy/phy.h> + +#include "phy-samsung-ufs.h" + +#define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL 0x728 +#define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1 +#define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0) + +#define PHY_TRSV_REG_CFG_AUTOV9(o, v, d) \ + PHY_TRSV_REG_CFG_OFFSET(o, v, d, 0x50) + +/* Calibration for phy initialization */ +static const struct samsung_ufs_phy_cfg exynosautov9_pre_init_cfg[] = { + PHY_COMN_REG_CFG(0x023, 0x80, PWR_MODE_ANY), + PHY_COMN_REG_CFG(0x01d, 0x10, PWR_MODE_ANY), + + PHY_TRSV_REG_CFG_AUTOV9(0x044, 0xb5, PWR_MODE_ANY), + PHY_TRSV_REG_CFG_AUTOV9(0x04d, 0x43, PWR_MODE_ANY), + PHY_TRSV_REG_CFG_AUTOV9(0x05b, 0x20, PWR_MODE_ANY), + PHY_TRSV_REG_CFG_AUTOV9(0x05e, 0xc0, PWR_MODE_ANY), + PHY_TRSV_REG_CFG_AUTOV9(0x038, 0x12, PWR_MODE_ANY), + PHY_TRSV_REG_CFG_AUTOV9(0x059, 0x58, PWR_MODE_ANY), + PHY_TRSV_REG_CFG_AUTOV9(0x06c, 0x18, PWR_MODE_ANY), + PHY_TRSV_REG_CFG_AUTOV9(0x06d, 0x02, PWR_MODE_ANY), + + PHY_COMN_REG_CFG(0x023, 0xc0, PWR_MODE_ANY), + PHY_COMN_REG_CFG(0x023, 0x00, PWR_MODE_ANY), + + PHY_TRSV_REG_CFG(0x042, 0x5d, PWR_MODE_ANY), + PHY_TRSV_REG_CFG(0x043, 0x80, PWR_MODE_ANY), + + END_UFS_PHY_CFG, +}; + +/* Calibration for HS mode series A/B */ +static const struct samsung_ufs_phy_cfg exynosautov9_pre_pwr_hs_cfg[] = { + PHY_TRSV_REG_CFG(0x032, 0xbc, PWR_MODE_HS_ANY), + PHY_TRSV_REG_CFG(0x03c, 0x7f, PWR_MODE_HS_ANY), + PHY_TRSV_REG_CFG(0x048, 0xc0, PWR_MODE_HS_ANY), + + PHY_TRSV_REG_CFG(0x04a, 0x00, PWR_MODE_HS_G3_SER_B), + PHY_TRSV_REG_CFG(0x04b, 0x10, PWR_MODE_HS_G1_SER_B | + PWR_MODE_HS_G3_SER_B), + PHY_TRSV_REG_CFG(0x04d, 0x63, PWR_MODE_HS_G3_SER_B), + + END_UFS_PHY_CFG, +}; + +static const struct samsung_ufs_phy_cfg *exynosautov9_ufs_phy_cfgs[CFG_TAG_MAX] = { + [CFG_PRE_INIT] = exynosautov9_pre_init_cfg, + [CFG_PRE_PWR_HS] = exynosautov9_pre_pwr_hs_cfg, +}; + +const struct samsung_ufs_phy_drvdata exynosautov9_ufs_phy = { + .cfg = exynosautov9_ufs_phy_cfgs, + .isol = { + .offset = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL, + .mask = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_MASK, + .en = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_EN, + }, + .has_symbol_clk = 0, +}; diff --git a/drivers/phy/samsung/phy-samsung-ufs.c b/drivers/phy/samsung/phy-samsung-ufs.c index dd9ab1519d83..602ddef259eb 100644 --- a/drivers/phy/samsung/phy-samsung-ufs.c +++ b/drivers/phy/samsung/phy-samsung-ufs.c @@ -347,6 +347,9 @@ static const struct of_device_id samsung_ufs_phy_match[] = { { .compatible = "samsung,exynos7-ufs-phy", .data = &exynos7_ufs_phy, + }, { + .compatible = "samsung,exynosautov9-ufs-phy", + .data = &exynosautov9_ufs_phy, }, {}, }; diff --git a/drivers/phy/samsung/phy-samsung-ufs.h b/drivers/phy/samsung/phy-samsung-ufs.h index 1532d239ff0e..b9b85d55a2d5 100644 --- a/drivers/phy/samsung/phy-samsung-ufs.h +++ b/drivers/phy/samsung/phy-samsung-ufs.h @@ -26,14 +26,17 @@ .id = PHY_COMN_BLK, \ } -#define PHY_TRSV_REG_CFG(o, v, d) { \ +#define PHY_TRSV_REG_CFG_OFFSET(o, v, d, c) { \ .off_0 = PHY_APB_ADDR((o)), \ - .off_1 = PHY_APB_ADDR((o) + PHY_TRSV_CH_OFFSET), \ + .off_1 = PHY_APB_ADDR((o) + (c)), \ .val = (v), \ .desc = (d), \ .id = PHY_TRSV_BLK, \ } +#define PHY_TRSV_REG_CFG(o, v, d) \ + PHY_TRSV_REG_CFG_OFFSET(o, v, d, PHY_TRSV_CH_OFFSET) + /* UFS PHY registers */ #define PHY_PLL_LOCK_STATUS 0x1e #define PHY_CDR_LOCK_STATUS 0x5e @@ -137,5 +140,6 @@ static inline void samsung_ufs_phy_ctrl_isol( } extern const struct samsung_ufs_phy_drvdata exynos7_ufs_phy; +extern const struct samsung_ufs_phy_drvdata exynosautov9_ufs_phy; #endif /* _PHY_SAMSUNG_UFS_ */
This patch adds to support phy-exynosautov9-ufs driver for ExynosAuto v9 series SoCs. The patch adds "samsung,exynosautov9-ufs-phy" compatible. Unlike previous exynos ufs phy, the chip uses 0x50 offset as PHY_TRSV_REG_CFG_OFFSET. Change-Id: I4ea333d4565af537c26a8876d1b27144eea3c3c6 Signed-off-by: Chanho Park <chanho61.park@samsung.com> --- .../bindings/phy/samsung,ufs-phy.yaml | 1 + drivers/phy/samsung/Makefile | 3 +- drivers/phy/samsung/phy-exynosautov9-ufs.c | 70 +++++++++++++++++++ drivers/phy/samsung/phy-samsung-ufs.c | 3 + drivers/phy/samsung/phy-samsung-ufs.h | 8 ++- 5 files changed, 82 insertions(+), 3 deletions(-) create mode 100644 drivers/phy/samsung/phy-exynosautov9-ufs.c