Message ID | 20211211021758.1712299-10-dmitry.baryshkov@linaro.org |
---|---|
State | Superseded |
Headers | show
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X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list <linux-phy.lists.infradead.org> List-Unsubscribe: <https://lists.infradead.org/mailman/options/linux-phy>, <mailto:linux-phy-request@lists.infradead.org?subject=unsubscribe> List-Archive: <http://lists.infradead.org/pipermail/linux-phy/> List-Post: <mailto:linux-phy@lists.infradead.org> List-Help: <mailto:linux-phy-request@lists.infradead.org?subject=help> List-Subscribe: <https://lists.infradead.org/mailman/listinfo/linux-phy>, <mailto:linux-phy-request@lists.infradead.org?subject=subscribe> Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" <linux-phy-bounces@lists.infradead.org> Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org |
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qcom: add support for PCIe0 on SM8450 platform
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diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index cd74b97b9018..e02d3c86e365 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -346,10 +346,20 @@ vreg_l6e_1p2: ldo6 { }; }; +&pcie0_phy { + status = "okay"; + vdda-phy-supply = <&vreg_l5b_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; +}; + &qupv3_id_0 { status = "okay"; }; +&qupv3_id_1 { + status = "okay"; +}; + &tlmm { gpio-reserved-ranges = <28 4>, <36 4>; };
Enable PCIe0 PHY on the SM8450 QRD device. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 10 ++++++++++ 1 file changed, 10 insertions(+)