From patchwork Sat Dec 18 14:10:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12686095 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0B25CC433FE for ; Sat, 18 Dec 2021 14:10:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=BeR0+BNQFQY2xm0nv7iZcfuNf6SNqvxWcItL0sR58p4=; b=A5ZrSBUIKNnBwG he3FLJn3wRjDiBC+H2Vloy0BMvD36+PJa8DwOei25ccGeGD7EiLOH+Zkipz6zvpzkzJCHwZviuOHF 4y8+TAdE1koToTrbom3XmMxcaROo1mQvH6K63kzIMsWumQibmB1n2dY5gxrmdMgo/M0FDZ/wl+qQU yDuS/zfkj3FKaAdJa0/6H1LKd0yjr0wm78iG3R1ZSNtHeY/OfkgIhVsfzfAPh/smM2jwC4pNIoIzH GTlYPHc7z2TI4fAGFVgX++QIwYCfxK6h04hIRFe5e8rRjD3vuYLlFUFYDjJm4Mektqs0dbQgdEmeV TrhFBAGqUrlZx1xtDr8g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1myaQ5-00DxcH-EV; Sat, 18 Dec 2021 14:10:41 +0000 Received: from mail-lj1-x229.google.com ([2a00:1450:4864:20::229]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1myaQ3-00Dxag-5C for linux-phy@lists.infradead.org; Sat, 18 Dec 2021 14:10:40 +0000 Received: by mail-lj1-x229.google.com with SMTP id a37so7861328ljq.13 for ; Sat, 18 Dec 2021 06:10:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qRTfrqHW0xadA2RxY5KGCJFnUIG7KdGyZAEOZqxM1/4=; b=iOFMgvFmIpQazIKOD+fY0GNlqpXkDSBwFpzoQ4uvjJ64moykTqP/vlc9GY3QIQCnwR h3R4we981InsGW5ogG19O7gY4XJgqgtSeyUJacOEoicd8AD0S+2GaBkfI2d6FJwRkOZL Yja2oeCfATNNfJUAlFefGo4UN9qXt1ZooeuSehSxFmvgOobNduDKNtK7umU4C02TfCGi 6UXVrwG8Sn/sHasr+OMkAUcvEpXj+NvGCdG5Uk+iaZvG3q1NHWiPdPlXklZ04DGsjBLM WKGyAmD63T025tAaFtMGnkSPLbgPuoWp0n0syyqoB/aiSObxbRNEaOsJptztXhxKd9An dvmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qRTfrqHW0xadA2RxY5KGCJFnUIG7KdGyZAEOZqxM1/4=; b=XTK8IIT3OEoDgDtJoPw0DlOO1RqbF7xPSw3aW6vMZkdwqLb17Dzvhf/vN/gZglZdnp UiNCOLiOV731bX7Fv801Ii8+LUUxsCTYwwUwo2YzmqX/nZBBv8CBN7UNPKNpdESO7gtk Kg4c8RybGJV54SqVmK4rWNJp+z4Q/rdqk3zGz6K+AiBKRaoH37fh1RiRRlluycxtQTta lfGntiPPN8uKOJwI/YgxmBPRacec62RWid0LMCe+jeaeIhB+N5GCOlUPrORpP4x/Z5ix TsZ3m4d/ZMTazdDXFz+KU7qvmOlQfgWe2WwqTsBPR/SK0AN6dCO09dhPjfIZ2iPH0IOT Gh9A== X-Gm-Message-State: AOAM533NyFdFKf+S3D7uuQjI/IE3c2RJKc4JwbF7h1R8FIni3UWkygGQ Nzg8HyoptoHAi8nC6OaCt2NdfA== X-Google-Smtp-Source: ABdhPJzVHKTobSj/zyyGnqgz32BOB6jYTAD4VZtQ4gDGrqlohwNzZfHV5hFrF+eBkhyKkljUKsZREg== X-Received: by 2002:a2e:9dcf:: with SMTP id x15mr7254742ljj.432.1639836637764; Sat, 18 Dec 2021 06:10:37 -0800 (PST) Received: from eriador.lan ([2001:470:dd84:abc0::8a5]) by smtp.gmail.com with ESMTPSA id c2sm145789lfh.189.2021.12.18.06.10.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Dec 2021 06:10:37 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Vinod Koul , Kishon Vijay Abraham I , Stanimir Varbanov , Lorenzo Pieralisi Cc: Bjorn Helgaas , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v5 5/5] PCI: qcom: Add SM8450 PCIe support Date: Sat, 18 Dec 2021 17:10:24 +0300 Message-Id: <20211218141024.500952-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211218141024.500952-1-dmitry.baryshkov@linaro.org> References: <20211218141024.500952-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211218_061039_226171_BDD58C65 X-CRM114-Status: GOOD ( 15.43 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org On SM8450 platform PCIe hosts do not use all the clocks (and add several additional clocks), so expand the driver to handle these requirements. PCIe0 and PCIe1 hosts use different sets of clocks, so separate entries are required. Signed-off-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson --- drivers/pci/controller/dwc/pcie-qcom.c | 57 ++++++++++++++++++++------ 1 file changed, 44 insertions(+), 13 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 55ac3caa6d7d..fe6ed1e0415a 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -161,7 +161,7 @@ struct qcom_pcie_resources_2_3_3 { /* 6 clocks typically, 7 for sm8250 */ struct qcom_pcie_resources_2_7_0 { - struct clk_bulk_data clks[7]; + struct clk_bulk_data clks[9]; int num_clks; struct regulator_bulk_data supplies[2]; struct reset_control *pci_reset; @@ -193,7 +193,10 @@ struct qcom_pcie_ops { struct qcom_pcie_cfg { const struct qcom_pcie_ops *ops; unsigned int pipe_clk_need_muxing:1; + unsigned int has_tbu_clk:1; unsigned int has_ddrss_sf_tbu_clk:1; + unsigned int has_aggre0_clk:1; + unsigned int has_aggre1_clk:1; }; struct qcom_pcie { @@ -1117,6 +1120,7 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; struct dw_pcie *pci = pcie->pci; struct device *dev = pci->dev; + unsigned int idx; int ret; res->pci_reset = devm_reset_control_get_exclusive(dev, "pci"); @@ -1134,18 +1138,22 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) if (ret) return ret; - res->clks[0].id = "aux"; - res->clks[1].id = "cfg"; - res->clks[2].id = "bus_master"; - res->clks[3].id = "bus_slave"; - res->clks[4].id = "slave_q2a"; - res->clks[5].id = "tbu"; - if (pcie->cfg->has_ddrss_sf_tbu_clk) { - res->clks[6].id = "ddrss_sf_tbu"; - res->num_clks = 7; - } else { - res->num_clks = 6; - } + idx = 0; + res->clks[idx++].id = "aux"; + res->clks[idx++].id = "cfg"; + res->clks[idx++].id = "bus_master"; + res->clks[idx++].id = "bus_slave"; + res->clks[idx++].id = "slave_q2a"; + if (pcie->cfg->has_tbu_clk) + res->clks[idx++].id = "tbu"; + if (pcie->cfg->has_ddrss_sf_tbu_clk) + res->clks[idx++].id = "ddrss_sf_tbu"; + if (pcie->cfg->has_aggre0_clk) + res->clks[idx++].id = "aggre0"; + if (pcie->cfg->has_aggre1_clk) + res->clks[idx++].id = "aggre1"; + + res->num_clks = idx; ret = devm_clk_bulk_get(dev, res->num_clks, res->clks); if (ret < 0) @@ -1210,6 +1218,9 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) goto err_disable_clocks; } + /* Wait for reset to complete, required on SM8450 */ + usleep_range(1000, 1500); + /* configure PCIe to RC mode */ writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE); @@ -1457,15 +1468,33 @@ static const struct qcom_pcie_cfg ipq4019_cfg = { static const struct qcom_pcie_cfg sdm845_cfg = { .ops = &ops_2_7_0, + .has_tbu_clk = true, }; static const struct qcom_pcie_cfg sm8250_cfg = { + .ops = &ops_1_9_0, + .has_tbu_clk = true, + .has_ddrss_sf_tbu_clk = true, +}; + +static const struct qcom_pcie_cfg sm8450_pcie0_cfg = { .ops = &ops_1_9_0, .has_ddrss_sf_tbu_clk = true, + .pipe_clk_need_muxing = true, + .has_aggre0_clk = true, + .has_aggre1_clk = true, +}; + +static const struct qcom_pcie_cfg sm8450_pcie1_cfg = { + .ops = &ops_1_9_0, + .has_ddrss_sf_tbu_clk = true, + .pipe_clk_need_muxing = true, + .has_aggre1_clk = true, }; static const struct qcom_pcie_cfg sc7280_cfg = { .ops = &ops_1_9_0, + .has_tbu_clk = true, .pipe_clk_need_muxing = true, }; @@ -1564,6 +1593,8 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-sdm845", .data = &sdm845_cfg }, { .compatible = "qcom,pcie-sm8250", .data = &sm8250_cfg }, { .compatible = "qcom,pcie-sc8180x", .data = &sm8250_cfg }, + { .compatible = "qcom,pcie-sm8450-pcie0", .data = &sm8450_pcie0_cfg }, + { .compatible = "qcom,pcie-sm8450-pcie1", .data = &sm8450_pcie1_cfg }, { .compatible = "qcom,pcie-sc7280", .data = &sc7280_cfg }, { } };